1. xerox 560 computer system - The UK Mirror Service

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BIRBRANCH ON INCREMENTING REGISTER(Word index alignment)BRANCH ON INCREMENTING REGISTER computes theeffective virtual address and then increments the contentsof general register R by 1. If the result is a negative value,the branch condition is satisfied and instruction executionthen proceeds with the instruction pointed to by the effectiveaddress of the BIR instruction. However, if the resultis zero or a positive va lue, the branch condition is not satisfiedand instruction execution proceeds with the next instructionin normal sequence.If the effective address of BDR is unavailable to the program(slave or master-protected mode) for instruction access andthe branch condition is satisfied, or if the effective addressof BDR is nonexistent, the basi c processor aborts executionof the BDR instruction and traps to location X'40'. In thiscase, the instruction address stored by the XPSD instructionin location X'40' is the virtual address of the aborted BDRinstruction. If the basi c processor traps because of instructionaccess protection, register Rwill contain the value thatexisted just before the BDR instruction. If a memory parityerror occurs due to the accessing of the instruction to whi chthe program is branching, the basic processor aborts executionof the BDR and traps to location X'4C r with register Runchanged.Affected: (R),(IA)(R) + 1 - RIf (R)O = 1, EVA 15_ 31-IAIf (R)O = 0, IA not affectedBALBRANCH AND LINK(Word index alignment)If the branch condition is satisfied and if the effective addressof BIR is either unavailable to the program (slave ormaster-protected mode) for instruction access or is nonexistent,the basi c processor aborts execution of the BIRinstruction and traps to location X'40'. In this case, theinstruction address stored by the XPSD instruction in locationX'40' is the virtual address of the aborted BIR instruction.If the basic processor traps because of instructionaccess protection, register R will contain the value thatexisted just before the BIR execution (i.e., updated instructionaddress). If a memory parity error occurs due to theaccessing of the instruction to which the program is branching,the basic processor aborts execution of the BIR andtraps to location X'4C' with register R unchanged.BDRBRANCH ON DECREMENTING REGISTER(Word index alignment)BRANCH AND LINK determines the effective virtual address,loads the updated instruction address (the virtual addressof the next instruction in normal sequence after theBAL instruction) into bit positions 15-31 of general registerR, clears bit positions 0-14 of register R to O's and thenreplaces the updated instruction address with the effectivevirtual address. Instruction execution proceeds with theinstruction pointed to by the effective address of the BALinstruction.The BAL instruction in real extended addressing will storethe full address of the next instruction in the specified Rregister. Positions 0-9 of the specified register will be setequal to zero.Affected: (R), (IA)BRANCH ON DECREMENTING REGISTER computes theeffective virtual address and then decrements the contentsof general register R by 1. If the result is a positive value,the branch condition is satisfied and instruction executionthen proceeds with the instruction pointed to by the effectiveaddress of the BDR instruction. However, if the resultis zero or a negative value, the branch condition is unsatisfiedand instruction execution proceeds with the next instructionin normal sequence.Affected: (R), (IA)(R) - 1 -RIf (R)O = 0 and (R)1-31 j 0, EVA 15 _ 31 -If (R)O = 1 and (R) = 0, IA not affectedIAIf the effective address of BAL is unavailable to the program(slave or master-protected mode) for instruction access andthe branch condition is satisfied, or if the effective addressof BAL is nonexistent, the basic processor aborts executionofthe BAL instruction and traps to location X'40' (nonallowedoperation trap). In this case, the instruction address storedby the XPSD instruction in location X'40' is the virtual addressof the aborted SAL instruction. If the basic processortraps because of instruction access protection, register R willcontain the updated instruction address. If a memory parityerror occurs due to the accessing of the instruction to whichthe program is branching, the basic processor aborts executionof the BA L and traps to location X'4C r with register Rchanged to the updated instruction address.108 Execute/Branch Instructions
CAll INSTRUCTIONSEach ofthe four CA LL instructions causes the basi c processorto trap to a specifi c location for the next instruction in sequence.The four CALL instructions, their mnemonics, andthe locations to wh i ch the basi c processor traps are:Instru ct ionTrapName Mnemonic LocationCALL 1 CAll X'48'CALL 2 CAL2 X'49'CALL 3 CAL3 X'4A'CALL 4 CAL4 X'4B'Each ofthese four trap locations must contain an EXCHANGEPROG RAM STATUS WORDS (XPSD) instruction. Executionof XPSD in the trap location for a CALL instruction is describedunder "Control Instructions, XPSD Exchange ProgramStatus Words". If the XPSD instruction is coded withbit position 9 set to 1, the next instruction (executed afterthe XPSD) is taken from one of 16 possible locations, asdesignated by the value in the R field of the CALL instruction.Each of the 16 locations may contqin an instructionthat causes the basic processor to branch to a specificroutine; thus, the four CALL instructions can be used toenter any of as many as 64 unique routines.The effective address of either a direct or indirect CALLinstruction is not used for a memory reference and, therefore,cannot cause a trap.CALI CALL 1(Word index alignment)CAL4 CALL 4(Word index al ignment)~CALL 4 causes the basic processor to trap to location X'4B'.CONTROL INSTRUCTIONSThe following privileged instructions are used to control thebasi c operating conditions-of the basic processor:Instruction NameLoad Program Status WordsExchange Program Status WordsLoad Register PointerMove to Memory Contro ILoad Real AddressLoad Memory StatusWaitRead DirectWrite DirectMnemonicLPSDXPSDLRPMMCLRALMSWAITRDWDIf execution of any control instruction is attempted whilethe basic processor is in the slave mode (i. e., while bit 8of the current program status words is a 1), the basi c processorunconditionally traps to location X'40' prior toexecuting the instruction.PROGRAM STATUS WORDSProgram status words have the following structure whenstored in memory:CALL 1 causes the basi c processor to trap to location X'48'.CAL2 CALL 2(Word index alignment)CA LL 2 causes the basi c processor to trap to location X '49'.BitPositionDesignationFunctionCAL3 CALL 3(Word index al ignment)0-34CCFRCondition codeFloating round5FSFloating significance mask6FZFloating zero maskCA LL 3 causes the basi c processor to trap to location X '4A '.7FNFloating normal ize maskCall Instructions/Control Instructions 109
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 67 and 68: Condition code settings:2 3 4 Resul
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 75 and 76: Condition code settings:2 3 4 Resul
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
Page 113: In the real extended addressing mod
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 135 and 136: Table 13.Description of I/o Instruc
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139 and 140: Table 16. Operational Status Byte (
Page 141 and 142: Table 19.Status Response Bits for A
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160: change the rate on the primary cons
Page 161 and 162: Location(hex) (dec)20 3221 3322 342
Page 163 and 164: Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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