Condition code settings:2 30 0 00 0 00 00 0000 0oo4 Result of PLM0 Word count> 0Word count = 00 Word count < CC,TVV = 1Word count = 0,TVV = 10 Space count = 0,word count < CC,f\N = 10Space count = 0,word count = 0,TW = 115Space count + CC > 2 -1,TS = 115o Space count + CC > 2 -1,word count < CC, TS = 1,and TW = 115Space count + CC > 2 -1,word count = 0, TS = 1,and TW = 11 InstructioncompletedInstru cti onabortedBit positions 16 through 31 of register R are treated as asigned integer, with negative integers in two's complementform (i. e., a fixed-point halfword). <strong>The</strong> modifier is algebraica Ily added to the top-of-stack address, subtractedfrom the space count, and added to the word count in thestack pointer doubleword. If, as a resu It of MSP, eitherthe space count or the word count would be decreased below0 or increased above 215_1, the instruction is aborted.<strong>The</strong>n, the basic processor either traps to location X'42' orsets the condition code to reflect the reason for aborting,depending on the stack limit trap inhibits.If the modification of the stack pointer doubleword can besuccessfully performed, MSP operates as follows:<strong>1.</strong> <strong>The</strong> modifier in register R is algebraically added to thecurrent top-of-stack address (SPD15-31)t, to point toa new top-of-stack location. (If the modifier is negative,it is extended to 17 bits by appending a highorder<strong>1.</strong>)2. <strong>The</strong> modifier is algebraically subtracted from the currentspace count (SPD33-47) and the result becomesthe new space count.3. <strong>The</strong> modifier is algebraically added to the currentword count (SPD49-63) and the result becomes the newword count.4. <strong>The</strong> condition code is set to reflect the new status ofthe new space count and new word count.Affected: (SPD), CCTrap: Push-down stack limitIf the instruction operation extends into a memory pageprotected either by the access protection codes or writelocks, the memory protection trap can occur. If theoperation extends into a memory region that is physicallynot present, the nonexistent memory address trap canoccur.If the address of the elements within the stack (pointed toby the top-of-stack address) is in the range 0 through 15,then the words to be !o(Jded ore taken from the genera!registers rather than from main memory. In this case, theresults wi II be unpredictable if any of the source registersare also used as destination registers.(SPD)15_31 + (R)16-31SE -SPD 15-31 t(SPD)33_47 - (R)16-31 - SPD 33_ 47(SPD)49_63 + (R)16_31- SPD 49-63Condition code settings:2 3 4 Resu!t of MSPo 0 0 0 Space count> 0,word count > O.MSPMODIFY STACK POINTER(Doubleword index alignment)MODIFY STACK POINTER modifies the stack pointerdcub!e\\'ord, !oceted at the effective doublewoid addiessof MSP by the contents of register R. Register R must havethe following format:000 Space count> 0,word count = O.o 0 0 Space count = 0,word count> O.ooSpace count = 0,word count = 0,,.,.. 1"\mOalTler = v.Instruction completedtFor real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it is a17-bit fi e Id (15-31).100 Push-Down Instructions (Non-Privileged)
If CC1, or CC3, or both CC1 and CC3 are lis after!,!xecution of MSP, the instruction was aborted but the pushdownstack limit trap was inhibited by the trap-on-spaceinhibit (SPD32), by the trap-on-word inhibit (SPD48), orboth. <strong>The</strong> condition code is set to reflect the reason foraborting as follows:2 3 4 Status of space and word counts- 0 Word count> O.Word count = O.- 0 - 0 ~ word count + modifier ~ 2 15 _<strong>1.</strong>- Word count + modifier < 0, and TW = 1 orword count + modifier> 215 _1, and TW = <strong>1.</strong>- ·0 Space count> O.Space count = O.o - 0 ~ space count - modifier < 2 15 _<strong>1.</strong>- Space count - modifier < 0, and TS = 1 orspace count - modi fi er > 215-1, and TS = <strong>1.</strong>PUSH-DOWN INSTRUCTIONS (PRIVILEGED)<strong>The</strong> <strong>computer</strong> has two privi leged push-down instructions:PUSH STATUS (PSS) and PULL STATUS (PLS). <strong>The</strong>se two instructionsand a Status Stack Pointer Doubleword faci litatethe storing (pushing) or loading (pulling) of a particularenvironment (contents of 16 general registers end ProgramStatus Words) into or out of a memory stack.STATUS STACK POINTER DOUBLEWORD<strong>The</strong> Status Stack Pointer Doubleword (SSPD) always residesin real memory locations 0 and 1 and is dedicated for PSSand PLS instructions. <strong>The</strong> format of parameters containedwithin the Status Stack Pointer Doubleword are as follows:programming considerations, the initial TSA is a specificvalue either as the result of a Mode 0, WRITE DIRECTinstruction or as the result of a PSS or PLS instruction, asdescribed below.During each PSS instruction, the memory stack is accessed28 times and the TSA is incremented by 1 before each access.<strong>The</strong> first memory stack location accessed has a relative addressequal to the initial TSA plus 1, ... , and the 28th memorystack location accessed has a relative address equal tothe initial TSA plus 28.. Although 28 memory stack locationsare accessed in an ascending sequence, on Iy 20 locations(as selected by the hardware) wi II contain the basicprocessor environment. Eight locations (whose contents aredesignated as "indeterminate", in Figure 12) are reservedand must not be used.For each PLS instruction, access to the memory stack iscontingent upon the Word Count as described subsequently.If access is permitted, the memory stack is accessed 28 timesand the TSA is decremented by 1 after each access. <strong>The</strong>first memory stack location accessed by a PLS instructionhas a relative address equal to the initial TSA, the secondmemory stack location accessed has a relative address equalto the initial TSA minus 1, ... , and the 28th memory stacklocation accessed has a relative address equal to the initialTSA minus 27. Although 28 memory stack locations areaccessed in a descending sequence, the hardware selectsand pulls the contents of only 20 locations containing validinformation, as shown in Figure 12, and loaded into thegeneral registers and PSWs ... <strong>The</strong> contents of eight locationsdesignated as indeterminate are ignored.If the terminal (last) TSA for a PSS or PLS instruction isnot modified by a Mode 0 WRITE DIRECT instruction, itmay be used as the initial TSA for a subsequent PSS or PLSinstruction. Each PSS instruction causes the memory stackto be increased by 28 word locations and each PLS instructioncauses the memory stack to be decreased by 28 wordlocations. <strong>The</strong> information is pushed and pulled on a last-in,first-out basis.Note: <strong>The</strong> PLS instruction is contingent upon the WordCount value, as described below.Real Memory Location 0:SPACE COUNTReal Memory Location 1:TOP OF STACK ADDRESS<strong>The</strong> Top of Stack Address (TSA) is always a 20-bit real memoryword address and is never mapped. Depending upon<strong>The</strong> Space Count field (bit positions 33-47) of the StatusStack Pointer Doubleword is a 15-bit counter that may containa value of 0 through 32,767. Depending upon programmingconsiderations, the initial Space Count is aspecific value either as the result of executing a Mode 0,WRITE DIRECT instruction or a PLS or PSS instruction.During a PSS instruction, the Space Count is decrementedby 1 for each word pushed into the memory stack. If theSpace Count is decremented to a value of zero before a"the words have been pushed, the PSS instruction continues(i. e., no trapping occurs). <strong>The</strong> environment is stored intoPush-Down Instructions (Privileged) 101
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
- Page 55 and 56: CC1 is unchanged by the instruction
- Page 57 and 58: Condition code settings:2 3 4 Resul
- Page 59 and 60: Example 2, odd R field value:Before
- Page 61 and 62: significance (FS), floating zero (F
- Page 63 and 64: next sequential register after regi
- Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
- Page 67 and 68: Condition code settings:2 3 4 Resul
- Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
- Page 71 and 72: original contents of register R, re
- Page 73 and 74: Instruction NameCompare HalfwordMne
- Page 75 and 76: Condition code settings:2 3 4 Resul
- Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
- Page 79 and 80: 4. At the completion of the left sh
- Page 81 and 82: Instruction NameFloating Subtract L
- Page 83 and 84: The following table shows the possi
- Page 85 and 86: Table 8.Condition Code Settings for
- Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
- Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
- Page 91 and 92: If no indirect addressing or indexi
- Page 93 and 94: Instruction NameMnemonicDesignation
- Page 95 and 96: Both byte strings are C bytes in le
- Page 97 and 98: of the destination byte that caused
- Page 99 and 100: again present, unti I a positive or
- Page 101 and 102: The new contents of register 7 are:
- Page 103 and 104: traps to location X'42 1 as a resul
- Page 105: If there is sufficient space in the
- Page 109 and 110: appropriate memory stack locations
- Page 111 and 112: II, EI) are generated by II ORing"
- Page 113 and 114: In the real extended addressing mod
- Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
- Page 117 and 118: The XPSD instruction' is used for t
- Page 119 and 120: If (I)1O = 0, trap or interrupt ins
- Page 121 and 122: For either memory map format and ei
- Page 123 and 124: initial value plus the initial valu
- Page 125 and 126: Table 9. Status Word 0Field Bits Co
- Page 127 and 128: READ INTERRUPT INHIBITSThe followin
- Page 129 and 130: Table 11.Read Direct Mode 9 Status
- Page 131 and 132: SET ALARM INDICATORThe following co
- Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
- Page 135 and 136: Table 13.Description of I/o Instruc
- Page 137 and 138: Table 15.Device Status Byte (Regist
- Page 139 and 140: Table 16. Operational Status Byte (
- Page 141 and 142: Table 19.Status Response Bits for A
- Page 143 and 144: If CC4 = 0, the MIOP is in a normal
- Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
- Page 147 and 148: The functions of bits within the DC
- Page 149 and 150: 4. Each unit-record controller (int
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- Page 153 and 154: Transfer in Channel. A control lOCO
- Page 155 and 156: Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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