1. xerox 560 computer system - The UK Mirror Service

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~ ___basic processor to execute the contents of the assignedinterrupt location as the next instruction. (Interrupt locationsare defined in II Physical Organization ll , later in thischapter.) The instruction address portion of the program status~ords (PSWs) remains unchanged unti I the instruction inthe interrupt location is executed.The instruction in the interrupt location must be one of thefollowing: XPSD, PSS, MTS, MTH, or MTW. If the executionof any other instruction in an interrupt location is attemptedas the result of an interrupt level advancing to theconditions for acknowledgment, an instruction exceptiontrap occurs.The use of the privileged instruction XPSD or PSS in an interruptlocation permits an interrupt-servicing routine tosave the entire current machine environment. If workingregisters are needed by the routine and additional registerblocks are avai lable, the contents of the current registerblock can be saved automatically with no time loss. Thisis accomplished by changing the value of the register pointer(using the LOAD REGISTER POINTER instruction), whichresults in the assignment of a new block of 24 registers tothe routine. The instruction LOAD REGISTER POINTER(LRP) is described in Chapter 3, IIControl Instructions ll •An interrupt level remains in the active state until it iscleared (removed from the active state and returned to thedisarmed or armed state) by the execution of the LPSD, PlS,or WD instruction. An interrupt-servicing routine can itselfbe interrupted (whenever a higher priority interrupt levelmeets all the conditions for becoming active) and then continued(after the higher priority interrupt is cleared). However,an interrupt-servicing routine cannot be interruptedby an interrupt of the same or lower priority as long as thehigher priority interrupt level remains in the active state.Any signals received by an interrupt level in the activestate are ignored. Norma lIy, the interrupt-servicing routineclears its interrupt level and transfers program controlback to the point of interrupt by means of an LPSD instructionwith the same effective address as the XPSD instructionin the interrupt location.transmission is delayed until the new inhibit states of thebasic processor are known; these states are transmitted tothe interrupt system so the latter can record the new basicprocessor status.DIALOGUE DURING AN INTERRUPT-EXITING SEQUENCEWhen the basic processor exits an interrupt-servicing routine,it must notify the interrupt system to move the interruptlevel associated with that routine from the active state toeither the armed or disarmed state. To do this it must gainaccess to the processor bus and the interrupt system, eitherof which maybe busy at the time access is requested. Whencommunication with the interrupt system is established, thebasic processor transmits information for setting the levelstate to armed or disarmed, and new inhibit states it has assumedas a result of the exit operation.PHYSICAL ORGANIZATIONUp to 62 interrupt levels are available, each with a uniquelocation (see Table 2) assigned in the System Control Processor,and with a unique priority. The basic processor canselectively arm, enable, or arm and enable any interruptlevel. The basic processor can also IItriggerll any interruptlevel (supply a signal at the same physical point where thesigna I from the externa I source wou Id enter the interruptlevel). The triggering of an interrupt permits testing specialsystems programs before the special systems equipmentis available. The basic processor also permits an interruptservicingroutine to defer a portion of the processing associatedwith an interrupt level by processing the urgentportion of an interrupt-servicing routine, triggering a lowerpriority level (for a routine that handles the less urgentpart), then clearing the high-priority interrupt level so thatother interrupts can occur before the deferred interrupt re-~_ :~ _____~~_..J~I"'V"~" ,~ 1"" v\.. ........ u.DIALOGUE BETWEEN THE BASIC PROCESSOR ANDTHE INTERRUPT SYSTEM DURING AN INTERUPTENTERING SEQUENCEWhen an interrupt level is ready to be moved to the activestate, a dialogue takes place between the interrupt systemand the basic processor. This dialogue takes place over theprocessor bus and involves the Processor Interface (PI) associatedwith the processor cluster of which the basic processoris a member. When the processor bus becomes avai lableand the basic processor is ut un interruptible point, the interruptsystem transmits the interrupt address to the basicprocessor. It initiates its interrupt actions (i.e., executesthe instruction in the interrupt location and services theinterrupt at the appropriate time to avoid race conditions,and communicates with the interrupt system with an indicationto move the level to the active state. This latterINTERRUPT GROUPSInterrupt levels are organized in standard group configurationsthat are connected in a predetermined and fixed prioritychain (see Table 2 and Figure 11). The priority of eachlevel within a group is fixed; the first level has the highestpriority and the last level has the lowest.INTERNAL INTERRUPTSStandard internal interrupts are provided with the systemand include all group D levels (interna I override t counterequaIs-zero, and I/O).32 Centra I ized Interrupts
AddressTable 2. Interrupt LocationsDIO AddressPSWsRegisterGroup Dec Hex Function Inhibit Group BitInternalOverride(optional)82 52 Counter 1 count pulse 1683 53 Counter 2 count pulse 1784 54 Counter 3 count pulse 1885 55 Counter 4 count pulse none 0 1986 56 Processor fault 2087 57 Memory Fault 21112 70 16113 71 17114 72 18115 73 19116 74 20External 117 75 External group 3 EI 3 21Override 118 76 (first 12 levels) 22119 77 23120 78 24121 79 25122 7A 26123 7B 2788 58 Counter 1 zero 22Counter- 89 59 Counter 2 zero CI 0 23Equals-Zero 90 5A Counter 3 zero 2491 5B Counter 4 zero 25I/O92 5C Input/Output 2693 50 Control panel 2794 5E Reserved II 0 2895 5F Reserved 29ExternalGroup 2(optional)96 60 16Externa I group 2 EI 2(first 12 levels)107 6B 27ExternalGroup 4(optional)128 80 16External group 4 EI 4(first 12 levels)139 8B .27ExternalGroup 5(optional)144 90 16I Externa I group 5 EI 5(fi rst 12 leve Is)155 9B 27Centralized Interrupts 33
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37: InterruptStateDisarmedArmed[$Waitin
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90:
DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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701 South Aviation BoulevardEI Segu
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