1. xerox 560 computer system - The UK Mirror Service

etry only for hardware errors that would otherwise resultin a basic processor trap to location X I 4C. Automatic instructionretry is inhibited if:1 • The current instruction is being executed as a trap orinterrupt instruction;2. The Register Altered bit (bit position 60) of the currentPSWs is set to 1 at the time of detection of thehardware error; or3. The Retry Inhibit bit (bit position 0) in the basic processorcontrol register is set to 1.INSTRUCTION EXCEPTION TRAPThe instruction exception trap occurs whenever the basicprocessor detects a set of operations that are called for inan instruction but cannot be executed because of either ahardware restriction or a previous event.The different conditions that cause the instruction exceptiontrap are:1. A processor-detected fau It that occurs during the executionof an interrupt or trap entry sequence. Aninterrupt or trap entry sequence is defined as the sequenceof events that consists of: (a) initiating aninterrupt or trap; (b) accessing the instruction in theinterrupt or trap location; and (c) executing that instruction,including the exchange of the programstatus words, if required. Note that instructions executedas a result of the interrupt or trap location arenot considered part of the entry sequence.2. An illegal instruction is found in the trap (not XPSD orPSS) or interrupt (not XPSD, PSS, MTB, MTH, MTW) locationwhen executing a trap or interrupt sequence.3. Bit positions 12-14 of the MOVE TO MEMORY CON­TROL (MMC) instruction are interpreted as an illegalconfiguration. This is, any configuration other than100, 010, 101, 001, or 011 •4. The set of operations, primarily doubleword and bytestringinstructions, that yield an unpredictable resultwhen an incorrect register is specified; this type offault is called "invalid register designation II and includesthe following instructions ll • tRegister 0 SpecifiedEdit Byte String (EBS)Floating Add Long (FAL)Floating Subtract Long (FSL)Floating Multiply Long (FML)Floating Divide Long (FDL)Translate Byte String (TBS)Translate and Test Byte String (TTBS)Edit Byte String (EBS)Move to Memory Control (MMC)TRAP CONDITION CODEThe Trap Condition Code (TCC) differentiates between thedifferent fault types. Table 4 shows the settings of the TCCfor the various faults that may be detected during a trap orinterrupt entry sequence.Table 4. TCC Setting for Instruction ExceptionTrap X I 4D 1Fault TypeTCCTrap or interrupt sequence and 1 1 1pro~essor-detected fault.Trap or interrupt sequence with 1 1 0invalid instruction.MMC configuration invalid. 0 0 1Invalid register designation. 0 0 0POWER ON TRAPPower On causes the basic processor to reset and then traptolocationX I 50 I • This will occur only following restorationof power after an interruption of less than 500 milliseconds.POWER OFF TRAPPower Off occurs at interruptible point. As source power isgoing off, the basic processor traps to location X 1511 andallows sufficient time for storage of information before thesystem becomes inoperable.1001Odd Register SpecifiedAdd Doub I ewo rd (A D)Subtract Doubleword (SD)tliInvalid register designation II faults do not set the PDFflag.PROCESSOR DETECTED fAULT fL~GThe Processor Detected Fault (PDF) flag aids in solving amultiple error problem. Most traps occur because of a dynamicprogramming consideration (i.e., overflow, attempteddivision by zero, incorrect use of an instruction or address,etc.) and recovery is easi Iy handled by another software44 Trap System