1. xerox 560 computer system - The UK Mirror Service

In the real extended addressing mode, a 20-bit address maybe used as a branch address via indexing or indirect addressing.If such a branch address, (A), is beyond the first128Kofreal memory, the instruction at (A) will be executed,but the next instruction address will be (A+1) in the original128K block unless (A) contains a branch instruction. Notethat with this exception all instructions executed in thereal extended addressing mode must lie in the first 128K ofrea I memory.EXUEXECUTE(word index alignment)BCSBRANCH ON CONDITIONS SET(Word index alignment)BRANCH ON CONDITIONS SET forms the logical product(AND) of the R field of the instruction word and the currentcondition code. If the logical product is nonzero, thebranch condition is satisfied and instruction execution proceedswith the instruction pointed to by the effective addressof the BCS instruction. However, if the logical productis zero, the branch condition is unsatisfi ed and instructionexecution then proceeds with the next instruction innormal sequence.EXECUTE causes the basic processor to access the instructionin the location pointed to by the effective address of EXUand execute the subject instruction. The execution of thesubject instruction, including the processing of trap andinterrupt conditions, is performed exactly as if the subjectinstruction were initially accessed instead of the EXU instruction.If the subject instruction is another EXU, thebasic processor executes the subject instruction pointed toby the effective address of the second EXU as describedabove. Such "chains" of EXECUTE instructions may be ofany length, and are processed (without affecting the updatedinstruction address) until an instruction other than EXU isencountered. After the final subject instruction is executed,inc:for"rtit"ln ..._.. __.. _-- Pypr"tit"ln ----------- nrt"lrpp,.lc;. r------_· with thp. np.xt instruction insequence after the initial EXU (unless the subject instructionis an LPSD or XPSD instruction, or is a branch instructionand the branch condition is satisfied).If an interrupt activation occurs between the beginning ofan EXU instruction (or chain of EXU instructions) and thelast interruptible point in the subject instruction, the BPprocesses the interrupt-servicing routine for the activeinterrupt level and then returns program control to the EXUinstruction (or the initial instruction of a chain of EXUinstructions), which is started anew. Note that a programis interruptible after every instruction access, including accessesmade with the EXU instruction, and the interruptibilityof the subject instruction is the same as the normalinterruptibility for that instruction.If a trap condition occurs between the beginning of an EXUinstruction (or chain of EXU instructions) and the completionof the subject instruction, the basic processor traps tothe appropriate trap location. The instruction address storedby the XPSD instruction in the trap location is the addressof the EXU instruction (or the initial instruction of a chainof EXU instructions).Affected: (lA) if CC n R f 0If CC n (1)8_11/0, EVA 15 - 31 -IAIf CC n (1)8-11 = 0, IA not affectedIf the R field of BCS is 0, the next instruction to be executedafter BCS is always the next instruction in ascendingsequence, thus effectively producing a "no operation IIinstruction.BCRBRANCH ON CONDITIONS RESET(Word index alignment)BRANCH ON CONDITIONS RESET forms the logical product(AND) of the R field of the instruction word and thecurrent condition code. If the logical product is zero, thebranch condition is satisfied and instruction execution thenproceeds with the instruction pointed to by the effectiveaddress of the BCR instruction. However, if the logicalproduct is nonzero, the branch condition is unsatisfied andinstruction execution then proceeds with the next instructionin normal sequence.Affected: (IA) if CC n R = 0If CC n (1)8-11 = 0, EVA 15_ 13-If CC n (1)8-11 10, IA not affectedIAAffected: Determined bysubject instructionT raps: Determined bysubject instructionCondition code settings: Determined by subject instruction.If the R field of BCR is 0, the next instruction to be executedafter BCR is always the instruction located at theeffective address of BCR, thus effectively producing a"branch unconditionally" instruction.Execute/Branch Instructions 107