LCWLOAD COMPLEMENT WORD0/Vord index alignment)If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after executionof LOAD ABSOLUTE WORD; otherwise, the BP executesthe next instruction in sequence.LOAD COMPLEMENT WORD loads the 32-bit two's complementof the effective word into register R. Fixed-pointoverflow occurs if the effective word is -231 (X'80000000')in which case the result in register R is -231 and CC2 is setto 1; otherwise, CC2 is reset to O.LCDLOAD COMPLEMENT DOUBLEWORD(Doubleword index alignment)Affected: (R),CC2,CC3,CC4-EW-RCondition code settings:2 3 4 Result in R- 0 0 0 Zero- 0 Negative- 0 0 Positive- 0 No fixed-point overflowoFixed-point overflowTrap: Fixed-pointoverflow.If CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after executionof LOAD COMPLEMENT WORD; otherwise, the BP executesthe next instruction in sequence.LOAD COMPLEMENT DOUBLEWORD forms the 64-bittwo's complement of the effective doubleword, loads the32 low-order bits of the resu It into register Ru 1, and thenloads the 32 high-order bits of the result into register R.If R is an odd value, the result in register R is the 32 highorderbits of the two's complemented doubleword. <strong>The</strong> conditioncode settings are based on the two's complement ofthe effective doubleword, rather than the final result inregister R.Fixed-point overflow occurs if the effective doubleword is_~3 (X'8000000000000000'), in which case the result inregisters Rand Ru1 is _~3 and CC2 is set to 1; otherwise,CC2 is reset to O.Affected: (R),(Rul),CC2,CC3,CC4[-ED]32_63 -Condition code settings:Ru1; [-ED] 0-31- RTrap: Fixed-point overflow2 3 4 Two's complement of effective doublewordLAWLOAD ABSOLUTE WORD0/Vord index alignment)- 0 0 0 Zero- 0 Negative- 0 0 PositiveIf the effective word is positive, LOAD ABSOLUTE WORD!oads the effective v.'ord into regi$ter R. If the effectiveword is negative, LAW loads the 32-bit two's complementof the effective word into register R. Fixed-point overflowoccurs if the effective word is -~ 1 (X'80000000'), inwhich case the result in register R is _2 31 , and CC2 is setto 1; otherwise, CC2 is reset to O.Affected: (R),CC2,CC3,CC4IEWI-RTrap: Fixed-point overflow- 0 No fixed-point overflowoFixed-point overflowIf CC2 is set to 1 and the fixed-point arithmetic trap mask(AM) is a 1, the BP traps to location X'43' after executionof LOAD COMPLEMENT DOUBLEWORD; otherwise, theBP executes the next instruction in sequence.Example 1, even R field value:Condition code settings:2 3 4 Resu I tin R- 0 0 0 Zero0 Nonzero- 0 No fixed-point overflow0 Fixed-point overflow (sign bit on)ED(R)(Ru 1)CCBefore executi on",,,,,.,,"' A t=,""'nn A n""~""r-'- /\ VIL..J"t..JU/07t-\O\...LJLrxxxxxxxxxxxxxxxxxxxxAfter execution·V"""I')AC:<strong>1.</strong>70nfl nr"l"'\cr:'/\ I VL..J"t.JVI U 7 ,...,1) ..... L..I<strong>1.</strong>.1X'FEDCBA98'X'765432 1 l'xOOl52 Load/Store Instructions
Example 2, odd R field value:Before executionAfter executionED X'0123456789ABCDEP X'0123456789ABCDEF'(R) xxxxxxxx X'FEDCBA98'CC xxxx x001LADLOAD ABSOLUTE DOUBLEWORD(Doubleword index alignment)of LOAD ABSOLUTE DOUBLEWORDi otherwise, the BPexecutes the next instruction in sequence.Example 1, even R field value:Before executionAfter executionED X'0123456789ABCDEF' X'0123456789ABCDEF'(R) xxxxxxxx X'01234567'(Ru1) = xxxxxxxx X'89ABCDEF'CC xxxx xOlOIf the effective doubleword is positive, LOAD ABSOLUTEDOUBLEWORD loads the 32 low-order bits of the effectivedoubleword into register Ru1, and then loads the 32 highorderbits of the effective doubleword into register R. If R isan odd value, the result in register R is the 32 high-orderbits of the effective doubleword. <strong>The</strong> condition code settingsare based on the effective doubleword, rather thanthe final result in register R.If the effective doubleword is negative, LAD forms the64-bit two's complement of the effective doubleword, loadsthe 32 low-order bits of the two's complemented doublewordinto register Ru 1, and then loads the 32 high-orderbits of the two's complemented doubleword into register R.If R is an odd value, the result in register R is the 32 highorderbits of the two's complemented doubleword. <strong>The</strong> conditioncode settings are based on the two's complement of.LL __ CC_ ... - _I II I .<strong>1.</strong>1 .1,... I I ••11'1:: I::1II::~IIVl:: UUUUII::VVUIU, IUHH:::r IrIun rne nnol resulT Inregister R.Fixed-point overflow occurs if the effective doubleword is-2 63 (X'8000000000000000'), in which case the result inregisters Rand Rul is -263 and CC2 is set to 1; otherwise,CC2 is reset to O.Affected: (R), (Ru 1),CC2,CC3,CC4Trap: Fixed-point overflowExample 2, even R field value:Before executionAfter executionED X' FEDCBA9876543210' X' FEDCBA987654321 0'(R) xxxxxxxx X'01234567'(Rul) = xxxxxxxx X'89ABCDFO'CC xxxx xOlOExample 3, odd R field value:Before executionAfter executionED - X'G.23456789ADCDEF X'G.23456789ADCDEF(R) xxxxxxxx X'01234567'CC xxxx xOlOLASLOAD AND SET(Word index alignment)IED1 32_ 63-Ru1i IEDI 0_ 31-RCondition code settings:2 3 4 Absolute value of effective doubleword- 0 0 0 Zeroo Nonzero- 0 No fixed-point overflowoFixed-point overflow (sign bit on)If CC2 is set to 1 and the fixed-point arithmeti c trap mask(AM) is a 1, the BP traps to location X'43' after executionLOAD AND SET loads the effective word into R. Ifthe effective address is equal to or greater than 16, aone is stored in the sign position of the effective location.If the effective address is equal to or less than 15(effective location is a general register), the sign bitremains unchanged. This instruction is used to interlockmultiple processors from the simultaneous execution ofcertai n secti ons of code or from the si mu I taneous accessto certain tables.Affected: (R), CC3, CC4EW-R1 -EW O ' if EA ~ 16Load/Store Instructions 53
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
- Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
- Page 10 and 11: Many operations are performed in fl
- Page 12 and 13: Rapid Context Switching. When respo
- Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
- Page 16: FAST MEMORYARITHMETIC AND CONTROL U
- Page 19 and 20: INFORMATION BOUNDARIESBasic process
- Page 21 and 22: (Maximumof eight)Core Core Core Cor
- Page 23 and 24: 3. Diagnostic logic. Each memory dr
- Page 25 and 26: eference address field of the instr
- Page 27 and 28: Instruction in memory:Instruction i
- Page 29 and 30: Real-extended addressing is specifi
- Page 31: Table 1. Basic Processor Operating
- Page 35 and 36: DesignationFunctionDesignationFunct
- Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
- Page 39 and 40: AddressTable 2. Interrupt Locations
- Page 41 and 42: is assumed to contain an XPSD or a
- Page 43 and 44: Table 3. Summary of Trap LocationsL
- Page 45 and 46: TRAP MASKSThe programmer may mask t
- Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
- Page 49 and 50: Instruction Name Mnemonic FaultDeci
- Page 51 and 52: subroutine. However, with certain c
- Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
- Page 55 and 56: CC1 is unchanged by the instruction
- Page 57: Condition code settings:2 3 4 Resul
- Page 61 and 62: significance (FS), floating zero (F
- Page 63 and 64: next sequential register after regi
- Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
- Page 67 and 68: Condition code settings:2 3 4 Resul
- Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
- Page 71 and 72: original contents of register R, re
- Page 73 and 74: Instruction NameCompare HalfwordMne
- Page 75 and 76: Condition code settings:2 3 4 Resul
- Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
- Page 79 and 80: 4. At the completion of the left sh
- Page 81 and 82: Instruction NameFloating Subtract L
- Page 83 and 84: The following table shows the possi
- Page 85 and 86: Table 8.Condition Code Settings for
- Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
- Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
- Page 91 and 92: If no indirect addressing or indexi
- Page 93 and 94: Instruction NameMnemonicDesignation
- Page 95 and 96: Both byte strings are C bytes in le
- Page 97 and 98: of the destination byte that caused
- Page 99 and 100: again present, unti I a positive or
- Page 101 and 102: The new contents of register 7 are:
- Page 103 and 104: traps to location X'42 1 as a resul
- Page 105 and 106: If there is sufficient space in the
- Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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