1. xerox 560 computer system - The UK Mirror Service

PORTS AND MEMORY BUSESA memory unit may contain two, four, or six ports, whichhave a fixed priority order for the resolution of access contention.Each port allows the memory unit to communicatevia a memory bus with a different external system (i.e., aprocessor cluster), which communicates with the memorybus via the Memory Interface (MI) (see Figure 4). Portsare numbered from 1 (top priority) to 6 (lowest priority).The selection logic is biased to select port 1 (the fast port)whenever the memory is quiescent. Thus performance isimproved for the Memory Interface (MI) connected to thatport, and hence to the processors connected to that MI.A memory reserve function insures proper execution of instructionsthat require guaranteed re-access to a memorylocation before a second processor can access it.Each port is equipped with an inhibit function that canbe activated from the Configuration Control Panel (seeChapter 6).Other major functions performed by the ports are:1. Address recognition.2. Address interleaving.The memory system is built up by interconnection of identicallynumbered ports of all memory units. Each interconnectingcable is called a memory bus, which is dedicatedto a single processor cluster (see Figure 4).PORT PRIORITYThe multi port structure a I lows two simultaneous requests formemory to be processed immediately if the requests arereceived on different ports for different memory units, andneither memory unit is busy. If a requested memory unitis busy or receives simultaneous requests, the memory portlogic selects the highest priority request first.Normally, all ports in a memory unit operate on the fixedpriority basis (the fast port has the highest priority and thehighest-numbered normal port the lowest). Thus, if a singlememory unit simultaneously receives requests on port 2 andport 4, port 2 has first access to the memory unit.Each port also has associated with it a high-priority linewhich, upon receiving a high-priority request, raises theportIs priority above that of all other ports except for anyhigher priority port, which also has a high-priority requeston its line.MEMORY INTERLEAVINGMemory interleaving is a hardware feature that distributessequential addresses into two independently operating memoryunits. Interleaving increases the probabil ity that a processor(i. e., basic processor, RMP, or MIOP) can gainaccess to a given memory location without encounteringinterference from another processor that is making sequentiaI requests.Two memory units of the same size can be two-way interleaved.Both memory units transform an incoming address,as follows:Size of EachMemory Unit32K16KAddress BitsInterchanged16 and 3117 and 31As a result of the address transformation, even incoming addressesare assigned to one memory unit and odd incomingaddresses to the other. Note that the incoming address (untransformed)is stored in the status register of the accessedunit in each cycle and is available as are other types of dynamicstatus information. (Interleaved memory units havetwo status registers, one in each of the units.)MEMORY UNIT STARTING ADDRESSEach memory unit is individually identified by starting addressswitches located on the Configuration Control Panel(see Chapter 6). These switches define the range of addressesthe memory unit responds to when servicing memoryrequests. All addresses, including the starting address, fora given memory unit are the same for all ports in that unit;that is, the address of a given word remains the same regardlessof the port used to access the word. The startingaddress of a memory uni t must be on a boundary equa I to amultiple of the size of the memory unit when two memoryunits (of the same size) are interleaved. The starting addressof one memory unit must be a multiple of the size ofthe two memory units together; the second memory unit musthave a starting address higher than that of its companion byits own size. Another way to say this is that the startingaddress for the combined units must be on a boundary equalto a multiple of the total size of the interleaved assembly.MAINTAINABILITY AND PERFORMANCEMemory maintainability is enhanced by the followingfeatures:1. Error detection. Each memory unit senses and remembersparity errors in the CMM data as well as parityerrors in the address word or the memory bus data, portselection errors, CMM selection error, and undefinedoperations. This status information is available to diagnosticprograms to facilitate error localization inspace and time of occurrence. The memor,' unit sensesand reports, but does not remember (for diagnostic purposes)a write lock violation.2. Modularity. For ease of replacement, the logic and storagecircuitry is packaged on modules that are removablefrom backpanelswithoutrequiring cable disconnectiol1s.16 Main Memory