level within the interrupt <strong>system</strong> (location X'5C) is armed,enabled, and not inhibited, the request wi II be processedby the BP in accordance with the priority that prevailswithin the interrupt <strong>system</strong>, the lOPs, and the I/O subchannelswithin an MIOP. <strong>The</strong> occurrence of an I/Ointerrupt because of a Stop command is reported as statusinformation (bit position 7 of register R) when the BPexecutes an AIO instruction (normally part of an I/Ohandling routine).Bi t posi ti ons 1-7 must be coded as zeros. Bi t posi ti ons 8-31and 40-63 are ignored; but it is recommended that they alsobe coded as zeros. Bit positions 32-39 are devi ce dependentand must be coded as specified in the appropriate peripheralreference manual.<strong>The</strong> Stop command is primari Iy used to terminate a commandchain for an unbuffered device, as illustrated in the firstexample given for the Transfer in Channel command. Notethat not all devices recognize the Stop order.I/O OPERATION PHASESThis section describes the genera I sequence of events (orphases) of any I/O operati on performed by an lOP, thefunction performed by the BP, lOP, and device controller/device during each phase, and a description of each typeof I/O operation including the applicability of parametersthat may be contained within a typical operational lOCO.For explanation purposes, each I/O operation has five majorphases: preparation, initiation, fetching, executing,and termination phase. Each phase is further describedbelow.PREPARATION PHASEBefore an I/O operation may be performed by an lOP, anappropriate command list must reside in main memory.INITIATION PHASEAssuming that an appropriate command list resides in mainmemory, an I/O operation is initiated only if the BP executesan SIO instruction that is accepted by the addressedlOP, device controller, and device. <strong>The</strong> acceptance orrejection of an SIO instruction is contingent upon conditionswithin the addressed lOP, device controller, anddevice and is indicated by the condition codes at the compietionof the SIO instruction. in either case, the BP isable to perform other instructions or tasks immediately afterexecuting an S10 instruction. (Refer to "SIO" instruction,Chapter 3, for further detai Is. )A successfu I 510 i nstructi on causes the addressed devi ce togo from the "ready" condition to the "busy" condition.FETCHING PHASEAlthough the services of the BP are not required duringthis phase, the BP may at any time execute either a TIO,TDV, or POL instruction without interfering with the I/Ooperation. However, excessive TIOs and TDVs may causea data overrun condition. <strong>The</strong> BP may also execute eitheran HIO or RIO instruction and stop the I/O operation. (AnHIO may leave the device in an unpredictable state; anRIO resets all controllers and devices on the addressed lOP. )As a result of accepting an SIO instruction, a command addressregister within the I/o subchannel (assigned to controlthe addressed device controller/device) is loaded withthe first command doubleword address, the content of GeneralRegister 0 when the 510 instruction is accepted. Atthe appropriate time, as determined by the priority, thedevice controller/device wi II request that the lOP accessmain memory and fetch the first word of the lOCO from aneven memory word location and increment the commandaddress register by one. <strong>The</strong> disposition of the first wordis dependent upon the contents of the first word.If the order field contains an I/o order for a devicecontroller/device, the content of the order field is eitherloaded into an order register within the appropriate devicecontroller/device or ignored (if the lOCO is being fetchedfor a data chained operation). If the order is a Read Backwardorder, a control flag is also set within the lOP whichallows the memory byte address to be decremented ratherthan incremented during the data transfer.For all orders (excluding the Transfer in Channel command,described below), the contents of bit positions 10-31 of thefirst word is loaded into a memory byte address register ofan appropriate I/o subchannel. Depending upon the I/Oorder, as described under "Execution Phase", the content ofthe memory byte address register may be used or ignored. Ifused, it specifies which memory word location is to be accessedand also the number of bytes of data {or control information}to be transferred into or out of that location.If the order field contains a Transfer in Channel command,it is recognized and executed immediately by the lOP. <strong>The</strong>content of bit positions 13=31 (designated as,the IInext com-=mand doubleword address" field) is loaded directly into thecommand address register. <strong>The</strong> Transfer in Channel commandis recognized and executed by the lOP, it is fetchedand executed as the result of fetching one word (rather thantwo), and it is transparent to the device controller/device(that is, it is executed without affecting the continuity ofan order that is data chained or an I/o operation that iscommand chained). Note: Although bit positions 0-3and 8-12 are currently ignored, it is recommended that theybe coded as zeros.Immediately after executing a Transfer in Channel command,the iOP wiii automaticaiiy fetch the first word or the nextlOCO as specified by the contents of the "next commanddoublewordaddress" field. If the order field ofthe next lOCOalso contains a Transfer in Channel command, the I/o operationis terminated immediately and the lOP enters a Halt statebecause an lOP control error (IOPCE) occurred (attemptingto execute two successive Transfer in Channel commands).148 I/O Operation Phases
Otherwise, the first word of the next lOCO is fetched andloaded as described above, and the second word is fetchedand loaded as described below.Since the Transfer in Channel command permits lOCOs tobe fetched from nonconsecutive locations, lOCOs containingTransfer in Channel commands may be included withina command list either to achieve command list continuityfrom one segment of a command list to another segment orto c?nstruct reiterative loops.For all lOCOs, except a control lOCO containing a Transferin Channel command, the lOP will automatically accessmain memory at the appropriate time, as determined by thepriority that prevails for accessing main memory, and fetchthe second word of the lOCO from the next consecutiveascending (odd) memory word location of the command listand increment the command address register by one. Thus,in all cases, after a fetching operation is completed, thecontent of the command address register wi II be an even(or doubleword) address.<strong>The</strong> contents of the second word are stored in appropriateregisters within the I/O subchannel. Depending upon theI/o order, as described under IIExecution Phase ll , the contentsof the various fields are either used or ignored.In addition to the lOP Control Error (IOPCE), the followingtypes of lIunusual end ll conditions may be detected duringthe fetching phase of an I/O operation: Memory AddressError (MAE), Control Check Fault (CCF), lOP Memory Error(IOPME), Bus Check Fault (BCF), and Memory InterfaceError (MIE). <strong>The</strong> detection of any of these errors causes theI/O operation to be terminated and if the IUE flag is set toa 1, an "unusual end" interrupt is requested.Depending upon the control function performed, certainControl orders may be a part of an I/o operationwhich may be continued after the Control order isexecuted. For example, an I/o operation involvinga magnetic tape unit may contain a Rewind order toreposition the tape prior to reading (or writing) one ormore records.Note: Within the context of the above explanation,the Control order is defined to be one thatdoes not transfer any information; thus, datachaining is precluded within the lOCO containingthe Control order; however, commandchaining may be specified. Control orders thatinvolve information transfers when executedare described below (see paragraphs 2 and 4).2. If the order specifies an input operation (e. g., Read,Read Backward, or Sense) and the Skip flag is codedas a 0, all parameters of the current lOCO may beapplicable. As a result of receiving an appropriateinput order, the devi ce transmits data (Read, or ReadBackward order) or information from special registers(Sense order) into data buffers of the associated I/Osubchannel within the lOP.Depending upon the priority that prevai Is for accessingmain memory, the lOP accesses a memory word location(as specified by the current memory byte address),transfers up to four bytes of data or i nformati on fromthe data buffers to a memory unit, provides a writekey, and increments (or decrements, if Read Backward",,.,.10,.' _._-'J +ho ...- ... mom",r" _..._., -,.- h.,+o ,..",1,.1roc:" --_._-- nn,.l -..- ,.Iorromon+c: --_._..._.. -- +ho ----byte count by one for each byte transferred out of thedata buffers.EXECUTION PHASEAlthough the services of the BP are not required duringthis phase, the BP may at any time execute either a TIO,TDV, or POL instruction without interfering with the I/ooperation. However, excessive testing may cause a dataoverrun condition. <strong>The</strong> BP may also execute either anHIO or P.IO instruction and stop the I/o operation. Afterthe second word of an lOCO is fetched and providing nolIunusual end ll condition was detected, the lOCO is executedas prescribed by the parameters contained therein. As afunction of the order and the status of the Skip flag, ifapplicable, an lOCO may be executed in one of five ways,as described below:<strong>1.</strong> Certain Control orders (e. g., Stop) may be executedby the device whi Ie the lOP monitors the operation inaccordance with the applicable control flags. Sinceno memory accesses and data (or information) transfersoccur, the contents of the memory byte address register,write key register, and byte count register maybe ignored. Other Control orders (e. g., Rewind for amagnetic tape unit) are listed and described in applicableXerox peripheral equipment reference manuals.<strong>The</strong> write key is evaluated against the preassignedwrite lock for the memory word location accessed.If the write key is valid for each memory word locationaccessed, the input operation continues, as describedabove, unti I it is completed or terminatedby an "unusual end" condition, other than Write LockViolation. If the write key is not valid, the memoryunit (1) generates and transmits a Write Lock Violation(WLV) signal to the lOP, (2) rejects the new data,and (3) does not disturb the previous contents of thememory word location accessed.If the write key is invalid for any memory word locationaccessed and the HTE flag is coded as a 1, the inputoperation is terminated immediately upon receipt of aWLV signal (see "Termination Phase ll ).If the HTE flag is coded as a 0, the memory unit mayaccept or reject the data or information, based on thewrite key/write lock evaluation for each memory wordlocation accessed, without affecting the operationswithin the lOP, device controller, or device. <strong>The</strong>input operation continues unti I either completed orterminated by an "unusual end" condition, other thana Write Lock Violation.I/O Operation Phases 149
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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Condition code settings:2 3 4 Resul
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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Condition code settings:2 3 4 Resul
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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- Page 121 and 122: For either memory map format and ei
- Page 123 and 124: initial value plus the initial valu
- Page 125 and 126: Table 9. Status Word 0Field Bits Co
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- Page 129 and 130: Table 11.Read Direct Mode 9 Status
- Page 131 and 132: SET ALARM INDICATORThe following co
- Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
- Page 135 and 136: Table 13.Description of I/o Instruc
- Page 137 and 138: Table 15.Device Status Byte (Regist
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- Page 141 and 142: Table 19.Status Response Bits for A
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- Page 149 and 150: 4. Each unit-record controller (int
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- Page 153: Transfer in Channel. A control lOCO
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- Page 159 and 160: change the rate on the primary cons
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- Page 163 and 164: Table 22.Diagnostic Control (P-Mode
- Page 165 and 166: at its normal rate (e. g., fixed du
- Page 167 and 168: SET LOW CLOCK MARGINSThis command c
- Page 169 and 170: BP STATUS AND NO.Th i s group of i
- Page 171 and 172: Input5MPri ntout5MFunctionStore X 1
- Page 173 and 174: 6. SYSTEM CONFIGURATION CONTROLPool
- Page 175 and 176: Table 25. Functions of Processor Cl
- Page 177: Table 26. Functions of Memory Unit
- Page 180 and 181: STANDARD 8-BIT COMPUTER CODES (EBCD
- Page 182 and 183: STANDARD SYMBOL-CODE CORRESPONDENCE
- Page 184 and 185: STANDARD SYMBOL-CODE CORRESPONDENCE
- Page 186 and 187: TABLE OF POWERS OF SIXTEEN II162564
- Page 188 and 189: HEXADECIMAL-DECIMAL INTEGER CONVERS
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- Page 198 and 199: APPENDIX B.GLOSSARY OF SYMBOLIC TER
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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