1. xerox 560 computer system - The UK Mirror Service

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Instruction in memory:Instruction in instruction register:Indi rect reference addresses:IIIr]-o -]]-1-]2-]-3-]4"']:....::-6-:-]:-]-:I-:-2-f ]-:-2-:3-1-::-4-~-5-:-2-:-1:-8-~9-:o--':,lo 0Contents of indirect reference address:Address used if bit 0 = 1:Displacement aligned for halfword indexing:Final effective address:Figure 9. Generation of Effective Virtual Address (Indirect Real-Extended Addressing)These are the register formats for byte-string instructions:Register Rul:Byte-string instruction:20-bit signed disp acement,sign extended before useRegister R:During real-extended addressing memory write protectionis invoked.Table 1 summarizes the addressing characteristics.24 Main Memory
Table 1. Basic Processor Operating Modes and Addressing CasesPSW BITMS MM MA Mode and Addressing Characteristics0 0 0 Master mode, unmapped, 17-bit calculations, real addressing (128K words, maximum).1 0 0 Slave mode, unmapped, 17-bit calculations, real addressing (128K words, maximum).0 0 1 Master mode, unmapped, 20-bit calculations, real-extended addressing, 17-bit instruction referenceaddress (instructions and indirect words in first 128K words only), indexed and indirect addresses are20 bits.1 0 1 Slave mode, unmapped, 20-bit calculations, real-extended addressing, 17-bit instruction referenceaddress (instructions and indirect words in first 128K words only), indexed and indirect addresses are20 bits.0 1 0 Master mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum), map to1M words, real (Sigma 6/7 map to first 128K words by virtue of loading map with three high-orderzeros for all pages).1 1 - Slave mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum), map to1M words, real (Sigma 6/7 map to first 128K words by virtue of loading map with three high-orderzeros for a II pages).0 1 1 Master-protected mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum),map to 1 M words, rea I (access protection invoked).INTERRUPT AND TRAP ENTRY ADDRESSINGAn instruction residing in an interrupt location (see "CentralizedInterrupt System" later in this chapter! and executedasthe directresultof an interruptsequence is definedas an interrupt instruction. Both conditions must be truesimultaneously. Thus an instruction in an interrupt locationis not an interrupt instruction if it is executed as the resultof a program branch to the interrupt location under normalprogram control. The only va I id interrupt instructions areXPSD, PSS, MTW, MTH, and MTB.Similarly, a trap instruction (see "Trap System", later inthis chapter) is defined as an instruction in a trap locationexecuted as a direct result of a trap condition. The onlyvalid trap instructions are XPSD and PSS.XPSD Address Calculations. Address calculations associatedwith XPSD instructions deviate from the standardforms. Two basic formats are used in XPSD instructions,depending on whether subjective or objective addressingis being used.Bit 10 of the XPSD instruction is the addressing type (AT)designator. In the circumstances described below, it designateswhether the reference address in the XPSD instructionis to be considered unconditionally as a 20-bit realaddress or whether the current mode of addressing calculationsis to be appl ied to it.Format 1:Format 2:Format 1 is used in these circumstances:1. Bit position 10 (AT) of the XPSD contains zero. In thisforma t the reference address is a 20-b it actua I address(i .e., no mapping). Note that this is true regardlessof whether the instruction is in a trap, interrupt, ornormal location and independent of the mode (mapped,unmapped, real-extended) of the current PSWs. If indirectaddressing is specified, the indirect word containsa 20-bit address with exactly the same properties.2. Bit position 10 (AT) oftheXPSD contains one, theinstructionis in a trap or interrupt location, the instructionis being executed as the result of a trap or interrupt,and the current mode of the PSWs is not rea I-extended.In this format, the reference address is a 20-bit actualMa i n Memory 25
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29: Real-extended addressing is specifi
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82:
Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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701 South Aviation BoulevardEI Segu
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