1. xerox 560 computer system - The UK Mirror Service

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If characteristic overflow occurs, the basic processor alwaystraps to location X'44 1 with the general registers unchangedand the condition code set to 0110 if the result is positive,or to 0101 if the result is negative.FLOATING-POINT MULTIPLY AND DIVIDEThe floating round (FR) and floating zero (FZ) mode controlbits determine the operation of floating-point multiplicationand division (if characteristic overflow does notoccur and division by zero is not attempted) as follows:FRFloating round:FR = 0No roundi ng speci fi ed.CONDITION CODES FORFLOATING-POINT INSTRUCTIONSThe condition code settings for floating-point instructionsare summarized in Table 8. The following provisions applyto all floating-point instructions:1. Undeflow and overflow detection apply to the finalcharacteristic, not to any "intermediate" value.2. If a floating-point operation results in a trap, the originacontents of all general registers remain unchanged.3. All shifting, truncation, and rounding are performedon absolute magnitudes. If the fraction is negative,then the two's complement is formed after shifting ortruncation.FZFR = 1Note:The results of floating multiplication anddivision instructions are to be rounded. Formultiply or divide operations, a normalizedproduct or quotient is produced, appendedby a guard digit. This wi II be an absolutevalue.The example above (under "Floating-PointAdd and Subtract") is not possible for multiplyand divide. Therefore, there is never a timepenalty for rounding.Floating zero:FZ = 0If the final result of a multiplication or divisionoperation cannot be expressed in normalizedform because of the characteristic beingreduced below zero, underflow has occurred.If underflow occurs, the result is set equal to"true" zero and the condition code is set to1100. If underflow does not occur, thecondition code is set to 0010 if the result ispbsitive, to 0001 if the resulT is negutive, orto 0000 if the result is zero.FASFLOATING ADD SHORT0Nord index alignment)The effective word and the contents of register R are loadedinto a set of internal registers and a low-order hexadecimalzero (guard digit) is appended to both fractions, extendingthem to seven hexadecimal digits each. FAS then forms thefloating-point sum of the two numbers. (See "FR Floatinground" under "Floating-Point Add and Subtract", if roundingapplies.) If no floating-point arithmetic fault occurs,the sum is loaded into register R as a short-format floatingpointnumber.Affected: (R), CC(R) + EW-RFALFLOATING ADD LONG(Doubleword index alignment)Trap: Floating-point arithmeticfaultFZ = 1Underflow causes the basic processor to trapto location X'44 1 with the contents of thegeneral registers unchanged. The conditioncode is set to 1110 if the result is positive,or to 1101 if the result is negative. If underflowdoes not occur, the resultant action isthe same as that for FZ = O.If the divisor is zero in a floating-point division; the basicprocessor always traps to location X'44 1 with the generalregisters unchanged and the condition code set to 0100. Ifcharacteristic overflow occurs, the basic processor alwaystraps to location X'44' with the general registers unchangedand the condition code set to 0110 if the result is positive,or to 0101 if the result is negative.The effective doubleword and contents of registers Rand Ru1are loaded into a set of internal registers.The operation of FAL is identical to that of FLOATINGADD SHORT (FAS) except that the fractions to be addedare each 14 hexadecimal digits long, guard digits are appendedto the fractions only if rounding is specified, and Rmust he an even value for correct results. If no flootingpointarithmetic fault occurs, the sum is loaded into registersRand Ru 1 as a long-format floating-point number.Affected: (R), (Rul), CC(R, Rul) + ED -R, RulTrap: Floating-point arithmetic fault, instructionexception78 Floating-Point Arithmeti c Instructions
Table 8.Condition Code Settings for Floating-Point InstructionsCondition Code1 2 3 4 Meaning If No Trap to Location X'44 1 Meaning If Trap to Location X'44 1 Occurs0 0 0 0 A x 0, 0/ A, or -A + A 0 *0 1 0 0 *@Divide by zero )0 1 0 1 * Overflow, N < 0 Always trapped0 1 1 0 * Ov~rflow, N >0 2 Postnorma 1- d = I, FN=O, d} "" h"ft no underflow• • • an no un er-0 1 0N > 0 I ZI ng SISN > 0 Izmg shifts flow with FZ= 11 1 0 0 Underflow wi th FZ = 0 and no trap by FS = 1 0Notes:
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83: The following table shows the possi
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
Page 113 and 114: In the real extended addressing mod
Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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