1. xerox 560 computer system - The UK Mirror Service

Table 13. Description of I/O Instructions (cont.)Bit Applicable InstructionsPosition (Mnemonics) Function and/or Description24 RIO, POlP, POlR, and AlO After the I/O address is generated, this bit is reserved and must be coded(cont.)with a zero.'"--- ~---- - ---------------------2531510, TIO, TDV, and HIO If the I/o instruction is addressed to a single-unit device controller (bit 24is a D), bits 25-31 represent one of 16 possible device controller addresses(X'OO' - X'OF'). There is no need to specify a device address.If the I/o instruction is addressed to a multiunit (e. g., magnetic tape) devicecontroller (bit 24 is a 1), bits 25-27 represent one of eight possible devicecontroller addresses (X'D' - X'7') and bits 28-31 represent one of 16 possibledevice addresses (X'D' - X'FI).Device controller addresses assigned to controllers within the same I/O channel(e. g., MIOP), must be mutually exclusive. Note that bit 24, which mustbe a 0 when addressing a single-unit device controller and a 1 when addressinga multiunit device controller, is not considered a part of the decive controlleraddr~ss. Thus, for example, if the device controller address X'D' is assignedto a multiunit device controller within an MIOP, no other device controller(single or multiunit) within that MIOP may have an address of XIOI.-- - - - -- - - - - - - - - - - - - - - - ---RIO, POlP, POlR, and AIOAfter the I/o address is generated, these bits are reserved and must be codedwith zeros.Table 14. I/o Status Information (Register R)Table 14. I/o Status Information (Register R) (cont.)BitBitPosition Significance Position SignificanceoReserved tBus Check Fault (BCF). This bit is set to 1if a discrepancy exists between the parityerror status in the memory unit and the lOPwhen an lOP is performing a main memoryread cycle. If the error occurs whi Ie accessingdata then the devi ce halt is controlledby the Halt-on-Transmission-Error flag (bitposition 36 of an I/O command doubleword).If the error occurs whi Ie fetching a command,the operation is terminated immediatelywith an "unusual end ll •Control Check Fault (CCF). This bit is setto 1 when a parity error occurs during a subchannelread operation within the MIOP.The operation terminates immediately withan "unusual end".3 tt Memory Interface Error (MIE). lOP Haltcondition is the same as a Bus Check Fault.4-1213-31Reserved tCurrent Command Doubl eword Address. The19 high-order bits of the main memory addressfrom which the command doubleword for theI/o operation currently being processed bythe addressed I/O subsystem is fetched.tTo ensure program compatibility with possible softwareand/or hardware enhancements, it is recommended thatreserved bits be treated as indeterminate and not used(L e, i masked),ttThe lOP unconditionally sets the Processor Fault Indicator(PFI) whenever a Bus Check Fault, Control CheckFault, Control Memory Fault, or Memory Interface Erroroccurs. The lOP fault status registerisset with status informationas listed under the POlP or POlR instructions.130 Tnput/Output Instruction