1. xerox 560 computer system - The UK Mirror Service

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MASTER MODEThe master/slave control bit (bit 8 of the PSWs) must containa zero for the basic processor to operate in mastermode. In th is mode the basic processor can perform a II ofits control functions and can modify any part of the system.The restrictions upon the basic processor1s operations in thismode are those imposed by the write locks on certain protectedparts of memory. It is assumed that there is a residentoperating system (operating in the master mode) thatcontrols and supports the operation of other programs (whichmay be in the master, master-protected, or slave mode).high-order bits contain zeros. The memory map always maps17-bit virtual addresses into 20-bit real addresses (seeIIMemory Address Control II, later in this chapter for a discussionof how the map is used).UNMAPPED MODEWhen the basic processor is operating in the unmapped mode,there is a direct one-to-one relationship between the effectivevirtual address of each instruction and the actual addressused to access main memory. (See II Rea I Addressing ll ,later in this chapter.)MASTER-PROTECTED MODEThe master-protected mode of operation provides additionalprotection for programs that operate in the master mode. Themaster-protected mode occurs when the basic processor isoperating in the master mode with the memory map in effectand the mode altered control bit (bit 61 of the PSWs) is on.In this mode the memory protection violation trap occurs(location X I 40 I , with CC4 = 1), as it does in all mappedslave programs, if a program makes a reference to a virtualpage to which access is prohibited by the current setting ofthe access protecti on codes.INFORMATION FORMATNomenclature associated with digital information within thecomputer system is based on functional and/or physical attributes.A "word" may be either a 32-bit instruction wordor a 32-bit data word.The bit positions of a word are numbered from 0 through 31as follows:SLAVE MODEThe slave mode of operation is the problem-solving modeof the basic processor. In this mode, access protectioncodes apply to the slave mode program if mapping is in effect,and all IIprivileged II operations are prohibited. Privilegedoperations are those relating to input/output and tochanges in the fundamental control state of the basic processor.All privileged operations are performed in themaster or master-protected mode by a group of privilegedinstructions. Any attempt by a program to execute a privilegedinstruction whi Ie the basic processor is in the slavemode results in a trap. The master/slave mode control bit(bit 8 of the PSWs) can be changed when the basic processoris in the master or master-protected mode. Nevertheless,a s!aVe mode program can gain direct access to certai!1 executiveprogram operations by means of CALL instructions.-The operations avai lable through CALL instructions are establishedby the resident operating system.A word can be divided into two 16-bit parts (halfwords) inwh ich the bit positions are numbered from 0 through 15 asfollows:A word can also be divided into four 8-bit parts (bytes) inwhich the bit positions are numbered 0 through 7 as follows:Two words can be combined to form a 64-bit element (adoubleword) in which the bit positions are numbered 0through 63 as follows:MAPPED MODEAlthough the memory map is located in the Memory Interface(MI), it functions as part of the basic processor. Thebasic processor communicates with memory through the MI.Mapping is effective for all the words of real memory, andis invoked when bit 9 (MM) of the PSWs contains a one.Memory mapping generates real page addresse:s from vir-tualaddresses. The memory map can be loaded with either11-bit real page addresses or 8-bit real page addresses bymeansofthe MOVE MEMORY CONTROL (MMC) privilegedinstruction (see Chapter 3, "Control Instructions "). Elevenbitreal page addresses are always provided for in the map,thus if 8-bit real page addresses are generated, the threeI : Least Signif~cant word: In " " "I~ ~ '" '" ~ " " ,,1« " " ,,:« " '" "I" ,; ,. ,,' ~ " " "1M,, " "In fixed-point binary arithmetic each element of informationrepresents nurneiical data as a signed integer (bit 0 representsthe sign, remaining bits represent the magnitude, andthe binary point is assumed to be just to the right of theleast significant or righi-most bit). Negative va lues arerepresented in two1s complement form. Other formats requiredfor floating-point and decimal instructions are describedin Chapter 3.12 Basic Processor
INFORMATION BOUNDARIESBasic processor instructions assume that bytes, halfwords,and doublewords are located in main memory according tothe following boundary conventions:1. A byte is located in bit positions 0 through 7, 8through 15, 16 through 23, and 24 through 31 of aword.2. A halfword is located in bit positions 0 through 15 and16 through 31 of a word.3. A doubleword is located such that bit positions 0 through31 are contained within an even-numbered word, andbit positions 32 through 63 are contained within thenext consecutive word (which is odd-numbered).Figure 3 illustrates these boundaries.DoublewordDoublewordWord (even address)Word (odd address)Word (even address)Word (odd address)Halfword 0 Halfword 1 Halfword 0 Halfword 1Halfword 0 Halfword 1 Halfword 0 Halfword 1Byte O! Byte 1 Byte 2!Byte 3 Byte 0 !Byte 1 Byte 2!Byte 3 Byte O! Byte 1 Byte 2!Byte 3 Byte 0 !Byte 1 Byte 2!Byte 3Figure 3. Information BoundariesINSTRUCTION REGISTERBitsDescriptionThe instruction register contains the instruction the basicprocessor is currently executing. The format and fields ofthe two general types of instructions (memory reference andimmediate operand) are described below. Specific formatsfor each instruction are given in Chapter 3.MEMORY REFERENCE INSTRUCTIONSInstructions that make reference to an operand in main memorymay have the following format:12-14 index register. If X contains zero, indexing will(cont.) not be performed; hence register 0 cannot be usedas an index register. (See "Address ModificationExample: Indexing (Real and Virtual Addressing) ",later in this chapter for a description of theindexing process.)15-31 Reference address. Th i s 17 -b i t fi e I d norma II y containsthe reference address of the instruction operand.The reference address is translated into aneffective virtual address in accordance with theaddressing type (real, real extended, or virtual)and the address modification required (direct!indirect or indexing). (See "Memory ReferenceAddresses" later in this chapter.)Bitso1-7DescriptionIndirect addressing. One level of indirect addressingis performed only if this bit position containsa one.Operation code. This 7-bit field contains the codethat designates the operation to be performed. Seethe inside front and back covers for complete listingsof operation codes.IMMEDIATE OPERAND INSTRUCTIONSImmediate operand type instructions are particularly efficientbecause the required operand is contained within theinstruction word. Hence, memory reference, indirect addressing,and indexing are not required.8-11 R field. For most instructions this 4-bit field designatesone of the first 16 general registers of thecurrent register block as an operand source, resultdestination, or both.12-14 X field. This 3-bit field designates one of generalregisters 1-7 of the current register block as anBitsoDescriptionBit position 0 must be coded with a zero. If itcontains a one, the instruction is interpreted as beingnonexistent. (See "Trap System ", later in thischapter. )Bas i c Processor 13
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
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Condition code settings:2 3 4 Resul
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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Condition code settings:2 3 4 Resul
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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