1. xerox 560 computer system - The UK Mirror Service

More documents

Recommendations

Info

PORTS AND MEMORY BUSESA memory unit may contain two, four, or six ports, whichhave a fixed priority order for the resolution of access contention.Each port allows the memory unit to communicatevia a memory bus with a different external system (i.e., aprocessor cluster), which communicates with the memorybus via the Memory Interface (MI) (see Figure 4). Portsare numbered from 1 (top priority) to 6 (lowest priority).The selection logic is biased to select port 1 (the fast port)whenever the memory is quiescent. Thus performance isimproved for the Memory Interface (MI) connected to thatport, and hence to the processors connected to that MI.A memory reserve function insures proper execution of instructionsthat require guaranteed re-access to a memorylocation before a second processor can access it.Each port is equipped with an inhibit function that canbe activated from the Configuration Control Panel (seeChapter 6).Other major functions performed by the ports are:1. Address recognition.2. Address interleaving.The memory system is built up by interconnection of identicallynumbered ports of all memory units. Each interconnectingcable is called a memory bus, which is dedicatedto a single processor cluster (see Figure 4).PORT PRIORITYThe multi port structure a I lows two simultaneous requests formemory to be processed immediately if the requests arereceived on different ports for different memory units, andneither memory unit is busy. If a requested memory unitis busy or receives simultaneous requests, the memory portlogic selects the highest priority request first.Normally, all ports in a memory unit operate on the fixedpriority basis (the fast port has the highest priority and thehighest-numbered normal port the lowest). Thus, if a singlememory unit simultaneously receives requests on port 2 andport 4, port 2 has first access to the memory unit.Each port also has associated with it a high-priority linewhich, upon receiving a high-priority request, raises theportIs priority above that of all other ports except for anyhigher priority port, which also has a high-priority requeston its line.MEMORY INTERLEAVINGMemory interleaving is a hardware feature that distributessequential addresses into two independently operating memoryunits. Interleaving increases the probabil ity that a processor(i. e., basic processor, RMP, or MIOP) can gainaccess to a given memory location without encounteringinterference from another processor that is making sequentiaI requests.Two memory units of the same size can be two-way interleaved.Both memory units transform an incoming address,as follows:Size of EachMemory Unit32K16KAddress BitsInterchanged16 and 3117 and 31As a result of the address transformation, even incoming addressesare assigned to one memory unit and odd incomingaddresses to the other. Note that the incoming address (untransformed)is stored in the status register of the accessedunit in each cycle and is available as are other types of dynamicstatus information. (Interleaved memory units havetwo status registers, one in each of the units.)MEMORY UNIT STARTING ADDRESSEach memory unit is individually identified by starting addressswitches located on the Configuration Control Panel(see Chapter 6). These switches define the range of addressesthe memory unit responds to when servicing memoryrequests. All addresses, including the starting address, fora given memory unit are the same for all ports in that unit;that is, the address of a given word remains the same regardlessof the port used to access the word. The startingaddress of a memory uni t must be on a boundary equa I to amultiple of the size of the memory unit when two memoryunits (of the same size) are interleaved. The starting addressof one memory unit must be a multiple of the size ofthe two memory units together; the second memory unit musthave a starting address higher than that of its companion byits own size. Another way to say this is that the startingaddress for the combined units must be on a boundary equalto a multiple of the total size of the interleaved assembly.MAINTAINABILITY AND PERFORMANCEMemory maintainability is enhanced by the followingfeatures:1. Error detection. Each memory unit senses and remembersparity errors in the CMM data as well as parityerrors in the address word or the memory bus data, portselection errors, CMM selection error, and undefinedoperations. This status information is available to diagnosticprograms to facilitate error localization inspace and time of occurrence. The memor,' unit sensesand reports, but does not remember (for diagnostic purposes)a write lock violation.2. Modularity. For ease of replacement, the logic and storagecircuitry is packaged on modules that are removablefrom backpanelswithoutrequiring cable disconnectiol1s.16 Main Memory
3. Diagnostic logic. Each memory driver module carrieslogic used exclusively for localizing faulty elementsin that module. The benefit derived from this diagnosticlogic depends on such external factors as the accessibilityto a module tester.Memory system performance depends on these factors:1. Access time of memory unit.2. Cycle time of memory unit.3. Type of cycle requested.4. Number of memory units.5. Interleaving.6 • Type of port (fast or norma I) selected.7. Self or mutual interference between memory requests.All these factors characterize not only memory performancebut a Iso system performance.Port access time and cycle time are essential memory speedcharacteristics pertaining to CMM operations.1. Port access time. This is the time interval measuredbetween the clock pulse that transmits an address wordfrom the Memory Interface (MI) to an idle memory unitand the clock pulse that translates a memory word fromthe same memory unit to the MI.2. Cycle time. Cycle time depends on the operation beingperformed and on the sequence of operation. Cycletime determines the maximum rate at which a memoryunit can accept requests.VIRTUAL AND REAL MEMORYVirtual memory is the address space available to an individualprogram. The maximum size of virtual memory is128K words, broken into as many as 256 pages of 512 wordseach distributed throughout the available pages of realmemory.Real memory corresponds to the physical memory, and its sizeis equal to the total number of words contained within allmemory units in the system. The size of real memory rangesfrom a minimum of 16K words to a maximum of 256K words.Note: Real memory address space is 1 mi Ilion words.MEMORY REFERENCE ADDRESSMemory locations 0 through 15 are not normally accessibleto the programmer because their memory addresses are reservedas register designators for "register-te-register" operations.Nevertheless an instruction treats any of thefirst 16 registers of the current register block as if it werea location in main memory. Furthermore, the register blockcan hold an instruction (or a series of as many as 16 instructions)for execution just as though the instruction (or instructions)were in main memory.The following terms are used in the various types of addressingdescribed in subsequent sections. See also Figure 5,which illustrates the control and data flow during addressgeneration.1. Instruction Address. This is the address of the nextinstruction to be executed. For real, real-extended,and virtual addressing the 17-bit instruction address iscontained within bits 15-31 of the program status words(PSWs) •2. Reference Address. Th is is the 17 -b i t or 20-b it addressassociated with any instruction (except that in a trapor interrupt location that has a 0 in bit position 10).For real, real extended, direct, and virtual addressing,the reference address is the address contained withinbits 15-31 of the instruction itself.The reference address may be modified by using indirectaddressing, indexing, and memory mapping. A referenceaddress becomes an effective virtual address afterthe indirect addressing and/or postindexing (if required)is performed.3. 20-Bit Trap or Interrupt Reference Address. If bit position10 of any instruction in a trap or interrupt locationcontains a 0, bits 12-31 of that instruction are used asa 20-b it reference address. Th is 20-b i t reference addresscan be modified only by using indirect addressing.This 20-bit reference address cannot be indexedor mapped. (See "Interrupt and Trap Entry Addressing",later in this chapter.)4. Direct Reference Address. If neither indirect addressingnor indexing is called for by the instruction (i. e.,if bit 0 and the X field contain zero), the referenceaddress of the instruction (as defined above) becomesthe effective virtual address. Direct addressing maybe used during real, virtual, or real extended addressingmodes, including trap and interrupt operations. Directaddressing during virtual addressing does not precludememory mapping.5. Indirect Reference Address. The 7-bit operation codefield of the instruction word format provides for as manyas 128 instruction operation codes, nearly all of whichcan use indirect addressing (except immediate-operandand byte-string instructions). If the instruction callsfor indirect addressing (bit position 0 contains a 1), thereference address (as defined above) is used to access aword location that contains the direct reference addressin bit positions 15-31, or bit positions 12-31 for certainreal extended addressing operations. The indirect addressingoperation is limited to one level, regardless ofthe contents of the word location pointed to by the referenceaddress field of the instruction. Indirect addressingoccurs before indexing; that is, the 17-bitMain Memory 17
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21: (Maximumof eight)Core Core Core Cor
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 67 and 68: Condition code settings:2 3 4 Resul
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74:
Instruction NameCompare HalfwordMne
Page 75 and 76:
Condition code settings:2 3 4 Resul
Page 77 and 78:
2 3 4 Result of ShiftCircular Shift
Page 79 and 80:
4. At the completion of the left sh
Page 81 and 82:
Instruction NameFloating Subtract L
Page 83 and 84:
The following table shows the possi
Page 85 and 86:
Table 8.Condition Code Settings for
Page 87 and 88:
PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90:
DSTDECIMAL STORE(Byte index alignme
Page 91 and 92:
If no indirect addressing or indexi
Page 93 and 94:
Instruction NameMnemonicDesignation
Page 95 and 96:
Both byte strings are C bytes in le
Page 97 and 98:
of the destination byte that caused
Page 99 and 100:
again present, unti I a positive or
Page 101 and 102:
The new contents of register 7 are:
Page 103 and 104:
traps to location X'42 1 as a resul
Page 105 and 106:
If there is sufficient space in the
Page 107 and 108:
If CC1, or CC3, or both CC1 and CC3
Page 109 and 110:
appropriate memory stack locations
Page 111 and 112:
II, EI) are generated by II ORing"
Page 113 and 114:
In the real extended addressing mod
Page 115 and 116:
CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118:
The XPSD instruction' is used for t
Page 119 and 120:
If (I)1O = 0, trap or interrupt ins
Page 121 and 122:
For either memory map format and ei
Page 123 and 124:
initial value plus the initial valu
Page 125 and 126:
Table 9. Status Word 0Field Bits Co
Page 127 and 128:
READ INTERRUPT INHIBITSThe followin
Page 129 and 130:
Table 11.Read Direct Mode 9 Status
Page 131 and 132:
SET ALARM INDICATORThe following co
Page 133 and 134:
INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 135 and 136:
Table 13.Description of I/o Instruc
Page 137 and 138:
Table 15.Device Status Byte (Regist
Page 139 and 140:
Table 16. Operational Status Byte (
Page 141 and 142:
Table 19.Status Response Bits for A
Page 143 and 144:
If CC4 = 0, the MIOP is in a normal
Page 145 and 146:
2 3 4 Meaningo 0 I/o address not re
Page 147 and 148:
The functions of bits within the DC
Page 149 and 150:
4. Each unit-record controller (int
Page 151 and 152:
Interrupt at Channel End (Bit Posit
Page 153 and 154:
Transfer in Channel. A control lOCO
Page 155 and 156:
Otherwise, the first word of the ne
Page 157 and 158:
Depending upon the characteristics
Page 159 and 160:
change the rate on the primary cons
Page 161 and 162:
Location(hex) (dec)20 3221 3322 342
Page 163 and 164:
Table 22.Diagnostic Control (P-Mode
Page 165 and 166:
at its normal rate (e. g., fixed du
Page 167 and 168:
SET LOW CLOCK MARGINSThis command c
Page 169 and 170:
BP STATUS AND NO.Th i s group of i
Page 171 and 172:
Input5MPri ntout5MFunctionStore X 1
Page 173 and 174:
6. SYSTEM CONFIGURATION CONTROLPool
Page 175 and 176:
Table 25. Functions of Processor Cl
Page 177:
Table 26. Functions of Memory Unit
Page 180 and 181:
STANDARD 8-BIT COMPUTER CODES (EBCD
Page 182 and 183:
STANDARD SYMBOL-CODE CORRESPONDENCE
Page 184 and 185:
STANDARD SYMBOL-CODE CORRESPONDENCE
Page 186 and 187:
TABLE OF POWERS OF SIXTEEN II162564
Page 188 and 189:
HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 196 and 197:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 198 and 199:
APPENDIX B.GLOSSARY OF SYMBOLIC TER
Page 200 and 201:
TermMeaningTermMeaningWKxWrite key
Page 202 and 203:
Table C-2. Memory Unit Status Regis
Page 204 and 205:
Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
Page 206:
701 South Aviation BoulevardEI Segu
show all

1. xerox 560 computer system - The UK Mirror Service

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?