Normally, bit positions 15-31 may be ignored insofar as theoperation of the MMC instruction is concerned. <strong>The</strong> resultsof the instruction are the same whether MMC is indirectlyor directly addressed. However,if MMC is indirectly addressedand the indirect reference address is nonexistent,the nona II owed operation trap (location X' 40 ' ) is activated.<strong>The</strong> R field, which must be coded with an even value, designatesan even-odd pair of general registers (R and Ru1)that contain additional control information required by theMMC instruction. If the R fi eld is coded with an odd va I uea trap to location X'4D ' (instruction exception trap) occurs.Depending upon the type of addressing, the contents ofregister R may be as follows:If MA = 0, contents of register Rare:<strong>The</strong> Control Start field (bit positions 15-20, 21, or 22)points to the beginning of the memory region controlled bythe registers to be loaded. <strong>The</strong> significance of this fieldis different for the 5 modes of MMC operations and is describedwithin each mode below.Affected: (R),(Ru1),memory controlstorageCONTROL IMAGELOADING THE MEMORY MAPT raps: Instruction exception,nonallowed operation.Each word of the memory map control image contains eitherfour a-bit page addresses or two ll-bit extended page addresses,as illustrated below:Typical memory map control image word (a-bit format):If MA = 1 and MM = 0, the contents of register Rare:Typical memory map control image word (ll-bit format):In either case, the Control Image Address is the virtual addressof a control word within the control image area to beloaded into a block of memory control registers, as specifiedby the contents of register Ru <strong>1.</strong>Depending upon the type of control image being loaded,the contents of register Ru 1 may be in one of the followingthree formats:Depending upon the memory map control image format, theinstruction format is one of the following:LMAPLOAD MAP (a-bit format)For loading memory map image (either a-bit or 11-bit format),contents of register Ru 1 are:LMAPRELOAD MAP REAL EXTENDED (ll-bit format)For loading 4-bit write lock images, contents of registerRu1 are:Depending upon the type of addressing, the format of registerR contents is one of the following:If MA = 0;For loading access protection or 2-bit write lock images,contents of register Ru 1 are:Map lma~e AddressIIf MA = 1 and MM = 0;<strong>The</strong> Count field (bit positions 0-7) specifies the numberofwords to be loaded from the control image area. If theinitial word count is zero, a word count of 256 is implied.114 Controi Instructions
For either memory map format and either type of addressing,the contents of register Ru 1 are:<strong>The</strong> instruction format for loading the access protectioncode is:MEMORY MAP LOADING PROCESS<strong>The</strong> initial map image address (in register R) is the virtualaddress of the first word of the memory map control image.<strong>The</strong> initial count, as contained in register Ru1 specifies theword length of the control image to be loaded. A wordcount of 64 (for 8-bit format) or 128 (for 11-bit format) issufficient to load an entire block of 256 memory map controlregisters. <strong>The</strong> memory map control registers are treatedas a circular set, with the first register following the last;thus, a word count greater than 64 (8-bit format) or 128(ll-bit format) causes the first registers to be overwritten.<strong>The</strong> initial value of the control start field of register Ru1points to the first page (512 words) of virtual addresses thatare to be controlled by the memory map control image beingloaded. <strong>The</strong> memory map control image is loaded into thememory map control registers one word at a time. As thecontents of each word are loaded into either two orfour memorymap control registers, the map image address is incrementedby 1, the word count is decremented by 1, and thevalue in the control start field is incremented either byfour(if the memory map control image is in the 8-bit format)or by two (if the memory map control image is in the 11-bitformat). <strong>The</strong> loading process continues until the word countis reduced to zero.When the load process is completed, the map image addressof register R contains a value equal to the sum of the initialmap image address plus the initial word count, the wordcount of register Ru1 has a value of zero, and the controlstart field of register Ru1 contains a value equal to the sumof the initial contents plus four or two times the initialword count.LOADING THE ACCESS PROTECTION CONTROLSCONTROL IMAGEEach access protection control image word contains sixteen2-bit fields; or, the access protection codes for 16 consecutivepages of virtual memory. Thus, the access protectioncontrol image for 128K word (256 page) virtual memory iscontained within 16 contiguous memory locations, designatedas the access protection control image area.<strong>The</strong> format of a typi ca I access protection control imageword is:Depending upon the type of addressing, the format of registerR contents is one of the following:IfMA=O;If MA = 1 and MM = 0;Ac cess Prote ionFor either type of addressing, the contents of register Ru1 are:ACCESS PROTECTION LOADING PROCESS<strong>The</strong> initial access protection control image address in registerR is the virtual address of the first word of the accessprotection control image.<strong>The</strong> initial count in register Ru1 specifies the word length ofthp rnnt .. nl ;rn,.,,.,p tn h., In,.,r<strong>1.</strong>,r1---- -----.- • • "--.;;;J- -- -- .--- ..... -_.A \A/1"\",..1 ,..""n+ "j: 1<strong>1.</strong>. :...."j:-- •• -.- --_••• _ •.• - ........-.~fi cient to load the entire block of 256 access protection controlregisters. <strong>The</strong> access protection control registers aretreated as a circular set, with the first register following thelast; thus, a word count greater than 16 causes the first-registersloaded to be overwritten.<strong>The</strong> initial value of the control start field of register Ru 1points to the first page (512 words) of virtual addresses thatare to be controlled by the access protection control imagebeing loaded. <strong>The</strong> access protection control image is loadedinto the access control registers one word at a time, .. thusloading the control registers for 16 consecutive pages with thecontents of each image word. As each image word is loaded,the access protection control imag~ address is incrementedby 1, the word count is decremented by 1, and the value inthe control start field is incremented by 4. <strong>The</strong> lo~dingprocess continues until the word count is reduced to O.When the loading process is completed, the parameters containedwithin registers Rand Ru1 have the following values:Access protectioncontrol image address = initial access protection controlimage address plus the initial wordcount.Count = O.Control Start =initial contents plus 4 times theinitial word count.Control Instructions 115
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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Condition code settings:2 3 4 Resul
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- Page 73 and 74: Instruction NameCompare HalfwordMne
- Page 75 and 76: Condition code settings:2 3 4 Resul
- Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
- Page 79 and 80: 4. At the completion of the left sh
- Page 81 and 82: Instruction NameFloating Subtract L
- Page 83 and 84: The following table shows the possi
- Page 85 and 86: Table 8.Condition Code Settings for
- Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
- Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
- Page 91 and 92: If no indirect addressing or indexi
- Page 93 and 94: Instruction NameMnemonicDesignation
- Page 95 and 96: Both byte strings are C bytes in le
- Page 97 and 98: of the destination byte that caused
- Page 99 and 100: again present, unti I a positive or
- Page 101 and 102: The new contents of register 7 are:
- Page 103 and 104: traps to location X'42 1 as a resul
- Page 105 and 106: If there is sufficient space in the
- Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
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- Page 111 and 112: II, EI) are generated by II ORing"
- Page 113 and 114: In the real extended addressing mod
- Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
- Page 117 and 118: The XPSD instruction' is used for t
- Page 119: If (I)1O = 0, trap or interrupt ins
- Page 123 and 124: initial value plus the initial valu
- Page 125 and 126: Table 9. Status Word 0Field Bits Co
- Page 127 and 128: READ INTERRUPT INHIBITSThe followin
- Page 129 and 130: Table 11.Read Direct Mode 9 Status
- Page 131 and 132: SET ALARM INDICATORThe following co
- Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
- Page 135 and 136: Table 13.Description of I/o Instruc
- Page 137 and 138: Table 15.Device Status Byte (Regist
- Page 139 and 140: Table 16. Operational Status Byte (
- Page 141 and 142: Table 19.Status Response Bits for A
- Page 143 and 144: If CC4 = 0, the MIOP is in a normal
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- Page 149 and 150: 4. Each unit-record controller (int
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- Page 155 and 156: Otherwise, the first word of the ne
- Page 157 and 158: Depending upon the characteristics
- Page 159 and 160: change the rate on the primary cons
- Page 161 and 162: Location(hex) (dec)20 3221 3322 342
- Page 163 and 164: Table 22.Diagnostic Control (P-Mode
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- Page 167 and 168: SET LOW CLOCK MARGINSThis command c
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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