1. xerox 560 computer system - The UK Mirror Service

The new contents of the destination byte string are:# 6 1 2 . 5 0 0 # # # 1 2 . 3 4 f) # # 0 3 5 ENDThe new condition code is:1011The new contents of register 1 are:X'xxx02013'Bit positions 15 through 31 of the SPD contain a 17-bitaddress field t that points to the location of the word currentlyat the top (highest-numbered address) of the operandstack. In a push operation, the top-of-stack addressis incremented by 1 and then an operand in a general registeris pushed (stored) into that location, thus becomingthe contents of the new top of the stack; the contents ofthe previous top of the stack remain unchanged. In a pulloperation, the contents of the current top of the stack arepulled (loaded) into a general register and then the topof-stackaddress is decremented by 1; the contents of thestack remain unchanged.PUSH-DOWN INSTRUCTIONS (NON-PRIVILEGED)The term "push-down processing ll refers to the programmingtechnique (used extensively in recursive routines) of storingthe context of a calculation in memory, proceeding with anew set of information, and then activating the previouslystored information. Typically, this process involves a reservedarea of memory (stack) into which operands arepushed (stored) and from which operands are pulled (loaded)on a last-in, first-out basis. The basic processor providesfor simplified and efficient programming of pushdownprocessing by means of the following non-privi legedinstructions:Instruction NamePush WordPull WordPush MultiplePull MultipleModify Stack Pointer_ ... _~T6r.1C ..... _pmNTI=R ........ _ nnnRI I=wnRn .....- ,---,I~PIl\.... -----_ .. _MnemonicPSWPLWPSMPLMMSPEach non-privileged push-down instruction operates withrespect to a memory stack that is defined by a doublewordlocated at effective address of the instruction. This doubleword,referred to as a stack pointer doubleword (SPD), hasthe following structure:I ~·I Space count I~I Word count I'32 '33 34 35136 37 ;8 39140 41 42 431« 45 46 47148 '49 50 5 d 52 53 54 55156 57 58 59160 61 62 63!tFor real extended mode of addressing this is a 20-bitfield (12-31); for real and virtual addressing modes it is a17-bit field (15-31).Bit positions 33 through 47 of the SPD, referred to as thespace count, contain a 15-bit count (0 to 32,767) of thenumber of word locations currently avai lable in the regionof memory allocated to the stack. Bit positions 49 through 63of the SPD, referred to as the word count, contain a 15-bitcount (0 to 32,767) of the number of words currently in thestack. In a push operation, the space count is decrementedby 1 and the word count is incremented by 1; in a pull operation,the space count is incremented by 1 and the wordcount is decremented by 1. At the beginning of all nonprivileged push-down instructions, the space count and theword count are each tested to determine whether the instructionwould cause either count field to be incremented abovethe upper limit of 2 15 _1 (32,767), or to be decrementedbelow the lower limit of O. If execution of the push-downinstruction would cause either count limit to be exceeded,the basic processor unconditionally aborts execution of theinstruction, with the stack, the stack pointer doubleword,and the contents of general registers unchanged. Ordinari Iy,the basic processor traps to location X'42' after abortinga push-down instruction because of impending stack limitoverflow or underflow, and with the condition code unchangedfrom the value it contained before execution ofthe instruction.However, this trap action can be selectively inhibited bysetting either (or both) of the trap inhibit bits in the SPDto 1.Bit position 32 of the SPD, referred to as the trap-on-space(TS) inhibit bit, determines whether the basic processor wi IItrap to location X'42' as a result of impending overflow orunderflow of the space count (SPD33-47)' as follows:TSoSpace count overflow/underflow actionIf the execution of a pull instruction would cause thespace count to exceed 2 15 _1, or if the execution of apush instruction would cause the space count to beless than 0, the basic processor traps to location X'42'with the condition code unchanged.Instead of trapping to location X'42', the basic processorsets CCl to 1 and then executes the next instructionin sequence.Bit position 48 of the SPD, referred to as the trap-on-word('f\N) inhibit bit, determines whether the basic processor96 Push-Down Instructions (Non-Privi leged)