1. xerox 560 computer system - The UK Mirror Service

Condition code settings:2 3 4 Result in RExample 2, odd R field value:Before executionAfter execution0 0 Zero0 Negative0 PositiveEW X'89ABCDEF' X'89ABCDEF'(R) XI FOFOFOFO ' X' 80AOCOEO'CC xxxx xxOlNote: Write locks protect memory and traps are not inhibitedduring the execution of LAS.LMLOAD MULTIPLE(Word index alignment)LSLOAD SELECTIVE(Word index alignment)Register Ru 1 contains a 32-bit mask. If R is an even value,LOAD SELECTIVE loads the effective word into register Rin those bit positions selected by a 1 in corresponding bitpositions of register Ru 1. The contents of register R are notaffected in those bit positions selected by a 0 in correspondingbit positions of register Rul.If R is an odd value, LS logically ANDs the contents ofregister R with the effective word and loads the result intoregister R. If corresponding bit positions of register Randthe effective word both contain lis, a 1 remains in registerR; otherwise, a 0 is placed in the corresponding bitposition of register R.Affected: (R), CC3, CC4If R is even, [EWn(Rul)] u [(R)n(Rul)]-RIf R is odd, EWn(R) -Condition code settings:R2 3 4 Result in R- 0 0 Zero.LOAD MULTIPLE loads a sequential set of words into a sequentia I set of registers, the set of words to be loaded beginswith the word pointed to by the effective address of LM,and the set of registers begins with register R. The set ofregisters is treated modulo 16 (i. e., the next register loadedafter register 15 is register 0 in the current register block).The number of words to be loaded into the general registersis determined by the setting of the condition code immediateybefore the execution of LM. (The desired value of thecondition code can be set with LCF or LCFI.) An initia Ivalue of 0000 for the condition code causes 16 consecutivewords to be loaded into the register block.Affected: (R) to (R-tCC-l)(EWL - R; (EWL + 1) - R+ 1), ... , (EWL -tCC-l) - R-tCC-lThe LM instruction may cause a trap if its operation extendsinto a page of memory that is protected by the accessprotection codes. A trap may also occur if the operationextends into a nonexistent memory region.If the effective virtual address of the LM instruction is inthe range 0 through 15, then the words to be loaded aretaken from the general registers rather than from main memnrv_./. Tn _...... thi~ - r:n~p ----- thp ...- ._-_ rp~lIlt~ ..- will ..... -- hp IInnrpriir:tnhlp _...... _-.-._-._ if .. nn\l _...,_.nfthe source registers are also used as destination registers.- 0 Bit 0 of register R is a 1.OBit 0 of register Ris a 0 andbitpositions 1-31of register R contain at least one 1.LCFILOAD CONDITIONS AND FLOATINGCONTROL IMMEDIATE(Immedi ate operand)Example 1, even R field value:r' ~,C vvBefore execution After execution- X'01234567 1 X'01234567 1(Ru 1) XI FFOOFFOO ' XI FFOOFFOO '(R) xxxxxxxx X'Ol xx45xx'CC xxxx xx 10If bit position 10 of the instruction word contains a 1, LOADCONDITIONS AND FLOATING CONTROL IMMEDIATEloads the contents of bit positions 24 through 27 of the instructionword into the condition code; however, if bit 10is 0, the condition code is not affected.If bit position 11 of the instruction word contains a 1,LCFI loads the contents of bit positions 28 through 31 ofthe instruction word into the floating round (FR), floating54 Load/Store Instructions