In the descriptions of the byte-string instructions, thefollowing abbreviations and terms are used:MBSMOVE BYTE STRING(Immediate Displacement, continue after interrupt)o Displacement, (1)12-3<strong>1.</strong>SAESACDASBSDBSSource address, (R)13-31Effecti ve source address, [(R) 13 -31 +(1) 12 -31} 3 -31<strong>The</strong> contents of bit positions 13-31 of register Rare added (right aligned) to the contents of bitposi tions 12-31 of the instruction word; the 19 loworderbits of the result are used as the effectivesource address.Count, (Ru1)0_7Destination address, (Ru1)13_31Source byte string, the byte' string that begins withthe byte location pointed to by the 19-bit effectivesource address and is C bytes in length (ifR is 0).Destination byte string, the byte string that beginswith the byte location pointed to by the destinati on address and is always C bytes in length.MOVE BYTE STRING copies the contents of the source bytestring (left to right) into the destination byte string. <strong>The</strong>previous contents of the destination byte string are destroyed,but the contents of the source byte string are notaffected unless the destination byte string overlaps thesource byte string.When the destination byte string overlaps the source bytestring, the resulting destination byte string contains one ormore repetitions of bytes from the source byte string. Thus,if a destination byte string of C bytes begins with thekth byte of a source byte string (numbering from 1), the firstk-1 bytes of the source byte string are duplicated in thedestination byte string x number of times, where x = C/{k-1).For example, if the destination byte string begins with thesecond byte of the source byte string, the first byte of thesource byte string is duplicated throughout the destinationbyte string.If both byte strings begin with the same byte (i. e., k = 1)and the R field of MBS is nonzero, the destination bytestring is read and replaced into the same memory locations.However, if both byte strings begin with the same byte andthe R field of MBS is zero, the first byte of the byte stringis duplicated throughout the remainder of the byte string(see "Case 111", below).Affected: (DBS), (R), (Ru1)(SBS) -DBSTRAPS BY BYTE-STRING INSTRUCTIONSByte-string instructions cause a trap if either of the addressedbyte strings come from memory pages that are protected byeither access protection or write locks. A trap also occursif elther byte stdng is fully or partly contoi!"'!ed with!!"'! memorypages that are physically not present. A check forthese access trap conditions is made prior to initiation ofany byte relocation or general register change. <strong>The</strong>se testsare performed for MOVE BYTE STRING and TRANS LATEBYTE STRING. <strong>The</strong> source and destination locations aretested for MOVE BYTE STRING; only the destination locationis tested for TRANSLATE BYTE STRING, since thereis no assurance that the translate table wi II be accessed inits entirety in the course of execution. If an access protectionviolation were to occur in trying to reach a byte inthe translate table or decimal digit strings during the courseof execution, then the instruction would trap and result inCi pCii-tiCilly executed condition. However, if the destinationbyte string does overlap the translation table, the registerswould be restored in such a manner that the instructioncould be restarted after the protection violation had beencorrected. When a trap occurs resulting in a partiallyexecuted instruction, the Register Altered indi cator wi"be set.If MBS is indirectly addressed, it is treated as a nonexistentinstruction. <strong>The</strong> basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contents ofregister R and the destination byte string unchanged. See"Traps by Byte String Instructions" (in this section) for othertrap conditions.Case I, even, nonzero R fi e Id (Ru 1 =R + 1)Contents of register R:Contents of register R+1:<strong>The</strong> source byte string begins with the byte location pointedto by the source address in register R plus the displacementin MBS; the destination byte string begins with the byte locationpointed to by the destiratior address in register R+l.88 Byte-String Instructions
Both byte strings are C bytes in length. When the instructionis completed, the destination and source addresses are eachincremented by C, and C is set to zero.Case II, odd R fi e Id (Ru 1 =R)Contents of register R:<strong>The</strong> source byte string begins with the byte location pointedto by the address in register R plus the displacement in MBS;the destination byte string begins with the byte locationpointed to by the destination address in register R. Bothbyte strings are C bytes in length. When the instruction iscompleted, the destination address is incremented by C,and C is set to zero.Condition code settings:2 3 4 Result of CBS- 0 0 Source byte string equals destination bytestring or initial byte count is equal to zero.- 0 Source byte string less than destination bytestring.o Source byte string greater than destinationbyte string.If CBS is indirectly addressed, it is treated as a nonexistentinstruction. <strong>The</strong> basic processor unconditionally abortsexecution of the instruction (at the time of operation codedecoding) and traps to location X'40' with the contentsof register R and the destination byte string unchanged.See "Traps By Byte String Instructions" (in this section) forother trap conditions.Case III, zero R field (Rul=l)Contents of register 1:Case I, even, nonzero R field {Rul=R+l}Contents of register R:<strong>The</strong> source byte string consists of a single byte, the contentsof the byte location pointed to by the displacement inMBS; the destination byte string begins with the byte locationpointed to by the destination address in register 1 andis C bytes in length. In this case, the source byte is duplicatedthroughout the destination byte string. When theinstruction is completed, the destination address is incrementedby C, and C is set to zero.Contents of register R+l:Ihe source byte string begins with the byte iocatlon pointedto by the source address in register R plus the displacementin CBS; the destination byte string begins with the byte locationpointed to by the destination address in register R+l.Both byte strings are C bytes in length.CBSCOMPARE BYTE STRING{Immediate displacement, continue after interrupt}Case II, odd R field (Ru l=R)Contents of register R:COMPARE BYTE STRING compares, as magnitudes, thecontents of the source byte string with the contents ofthe destination byte string, byte by corresponding byte,beginning with the first byte of each string. <strong>The</strong> comparisoncontinues unti I the specified number of bytes havebeen compared or unti I an inequality is found. When CBSis terminated, CC3 and CC4 are set to indicate the resultofthe last comparison. If the CBS instruction terminates due toinequality, the count in register Rul is one greater than thenumber of bytes remaining to be compared; the source addressin register R and the destination address in register Rulindicate the locations of the unequal bytes.Affected: {R}, (Rul), CC3, CC4(SBS) : (DBS)<strong>The</strong> source byte string begins with the byte location pointedto by the address in register R plus the displacement in CBS;the destination byte string begins with the byte locationpointed to by the destination address in register R. Bothbyte strings are C bytes in length.Case III, zero R field (Rul=l)Contents of register 1:<strong>The</strong> source byte string consists of a single byte, the contentsof the location pointed to by the displacement in CBS;Byte-String Instructions 89
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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- Page 45 and 46: TRAP MASKSThe programmer may mask t
- Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
- Page 49 and 50: Instruction Name Mnemonic FaultDeci
- Page 51 and 52: subroutine. However, with certain c
- Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
- Page 55 and 56: CC1 is unchanged by the instruction
- Page 57 and 58: Condition code settings:2 3 4 Resul
- Page 59 and 60: Example 2, odd R field value:Before
- Page 61 and 62: significance (FS), floating zero (F
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- Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
- Page 67 and 68: Condition code settings:2 3 4 Resul
- Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
- Page 71 and 72: original contents of register R, re
- Page 73 and 74: Instruction NameCompare HalfwordMne
- Page 75 and 76: Condition code settings:2 3 4 Resul
- Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
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- Page 81 and 82: Instruction NameFloating Subtract L
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- Page 85 and 86: Table 8.Condition Code Settings for
- Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
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- Page 91 and 92: If no indirect addressing or indexi
- Page 93: Instruction NameMnemonicDesignation
- Page 97 and 98: of the destination byte that caused
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- Page 103 and 104: traps to location X'42 1 as a resul
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- Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
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- Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
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- Page 129 and 130: Table 11.Read Direct Mode 9 Status
- Page 131 and 132: SET ALARM INDICATORThe following co
- Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
- Page 135 and 136: Table 13.Description of I/o Instruc
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- Page 141 and 142: Table 19.Status Response Bits for A
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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