1. xerox 560 computer system - The UK Mirror Service

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Table 3. Summary of Trap Locations (cont.)LocationsPSWsDec. Hex. Function Mask Bit Time of Occurrence Trap Condition Code72 48 CALLl None At instruction decode. Equal to R field ofCALL instruction.73 49 CALL2 None At instruction decode. Equal to R field ofCALL instruction.74 4A CALL3 None At instruction decode. Equal to R field ofCALL instruction.75 4B CALL4 None At instruction decode. Equal to R field ofCALL instruction.76 4C Hardware error trap None At time of basic processor detec- TCC1, 2, 3 = 0tion (the PDFt flag wi II be set).TCC4 = 0 if parityerror on genera I registeror internal controlregister.TCC4 = 1 if otherhardware errors.77 4D Instruction exception None (The PDF t flag will be set.) Set TCC3 if MMC contrapfiguration illegal;set TCC = X·C· if trapor interrupt sequencewith illegal instruction;set TCC = X·F· if trapor interrupt sequenceand processor detectedfault;set TCC4 if invalidregister designation(odd register on AD,SD, FAL, FSL, FML,FDL, TBS, TTBS, EBS,and register 0 on EBS).78 4E Reserved79 4F Reserved80 50 Power on Interruptible point.81 51 Power off Interruptible point.tSee IIProcessor Detected Faults ll ,later in this chapter.38 Trap System
TRAP MASKSThe programmer may mask the four trap conditions describedbelow in the program status words (PSWs) or the stack pointerdoubleword, as appropriate; other traps cannot be masked.1. The push-down stack I imit trap is masked within thestack pointer doubleword for each individual stack.2. The fixed-point overflow trap is masked in bit position11 (AM) of the PSWs. If this bit position containsa zero, the trap is allowed to occur; if bit 11 containsa zero, the trap is not allowed to occur. AM can bemasked by operator intervention, or by execution ofthe XPSD, PSS, PLS, or LPSD privileged instructions.3. The floating-point significance check trap is maskedby a combination of the floating significance (FS),floating zero (FZ), and floating normalize (FN) modecontrol bits in the PSWs (see IIFloating-Point ArithmeticFault Trapll, later in this chapter). FS, FZ, andFN can be set or cleared by the execution of any ofthe following instructions:LOAD CONDITIONS AND FLOATING CONTROL (LCF)LOAD CONDITIONS AND FLOATING CONTROL IMMEDIATE (LCFI)EXCHANGE PROGRAM STATUS WORDS (XPSD)LOAD PROGRAM STATUS WORDS (LPSD)PUSH STATUS (PSS)PULL STATUS (PLS)4. The decimal arithmetic fault trap is masked by bit position10 (DM) of the PSWs. If DM contains a one,the trap is allowed; if DM contains a zero, the trap isnot allowed. DM can be masked by execution ofthe X PSD, PSS, PLS, or LPSD privi leged instruction.with the condition code bits (CC1-CC4) of the new PSWswhen loading CC1-CC4. See also IIInstruction ExceptionTrapll later in this chapter for more information on the trapcondition code.NONALLOWED OPERATION TRAPThe attempt to perform a nonallowed operation alwayscauses the basic processor to abort the instruction being executedwhen the nonallowed operation is detected and toimmediately execute the XPSD or PSS instruction in trap locationX 1 40 1 • A nonallowed operation cannot be masked.NONEXISTENT INSTRUCTIONAny instruction that is not standard is defined as nonexistent.This includes immediate operand instructions thatspecify indirect addressing (a one in bit 0 of the instruction).If a nonexistent instruction is detected, the basic processortraps to location X 140 1 when the nonexistent instruction isdecoded. No general registers or memory locations arechanged; the PSWs point to the instruction trapped. Withrespect to the condition code and instruction address fieldsof the program status words, the operation of the XPSD orPSS in location X 140 1 is as follows:1. Store the current PSWs. The condition codes stored arethose that existed at the end of the last instructionprior to the nonexistent instruction.2. Store the 16 general registers of the current registerblock if instruction in trap location is a PSS.3. Load the new PSWs.4. Modify the new PSWs.TRAP CONDITION CODEFor the push-down stack limit trap, fixed-point overflowtrap, floating-point fault trap, and decimal fault trap, thenormal condition code register (CC 1-CC4) is loaded withmore detai led information about the trap condition justbefore the trap occurs. These condition codes are saved aspart of the old program status words when the XPSD or PSSinstruction is executed in response to the trap.For the nona I lowed operation trap, watchdog timer runouttrap, hardware error trap, instruction exception trap, andCALL trap, a special register (trap condition codes TCC1-TCC4) is loaded just before the trap occurs. When theX PSD or PSS instruction is executed in response to the trap,this register is added to the new program address if bit 9(MM) contains a one; TCC 1-TCC4 are also logically OReda. Set CCl to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the X PSD or PSS instructioncontains a one, the program counter is incremented by eight. If AI contains a zero, theprogram counter remains unchanged from the valueloaded from memory.NONEXISTENT MEMORY ADDRESSAny attempt to access a nonexistent memory address causesa trap to location X l 40 1 at the time of the request for memoryservice. A nonexistent memory address condition isdetected when an actual address is presented to the memoryT rap System 39
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 14 and 15: 2. SYSTEM ORGANIZATIONThe elements
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43: Table 3. Summary of Trap LocationsL
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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701 South Aviation BoulevardEI Segu
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