1. xerox 560 computer system - The UK Mirror Service

More documents

Recommendations

Info

POLP and POLR INSTRUCTIONSThe R field of these two instructions always specifiesa generalregister (including register 0) that may receive up to16 bits of fault status information from an addressed BP,RMP or MIOP. Each bit indicates the presence (l) or absence(O) of a specific fault condition within the polledprocessor (as listed in Table C-1). Note that the informationrepresented by a particular bit is also dependent uponthe type of processor polled (e. g., bit 18 may indicate amemory parity error in the BP or a control check faultwithin an MIOP).AlO INSTRUCTIONFor this instruction, if the R field has a value of 0, nostatus information is requested nor loaded. If the R fieldhas a value of X'l' through X'F', the specified register mayreceive one word of I/o information pertaining to an I/Ointerrupt.BitPositionTable 18. lOP Status Byte (cont.)Significance8 the byte count has been reduced to zero), or(cont.) is caused by the device controller receivinga count done signal before channel end (orend of record): e. g., count done before 80columns have been read from a card.When set to a I, the incorrect length bit, byitself, always signifies that an "incorrectlength" condition has occurred. If the SILflag (bit 38 of the I/O command doubleword)is coded with a 0, the detected incorrectlength condition is to be interpreted as anerror condition. If the SIL flag is coded witha 1, the detected incorrect length conditionis to be interpreted as anonerror condition.If an incorrect length condition is to result ina device halt, the SIL flag must be coded witha 0 and the HTE flag (bit 36 of the I/O commanddoubleword) must be coded with a 1.Device and Device Controller Status Byte. Bits 0-7 of thestatus word obtained by an AIO instruction from a respondingI/o subsystem are unique to the device and devicecontroller. These bits are described in the applicable peripheraldevice reference 'manual.9Transmission Data Error. This bit is set to 1if, since the last accepted SIO instructionaddressed to this subchannel, the device controlleror lOP detected a parity error or dataoverrun in the transmitted information. Adevice halt occurs as a result of a transmissiondata error only if the HTE flag of the I/Ocommand doubleword is coded with a 1.lOP Status Byte. Bits 8-15 indicate the presence (1) orabsence (0) of various operation errors and interrupts thatmay have occurred during an I/O operation. The functionsof individual bits within the lOP Status Byte are describedin Table 18.Table 19 is a summary description of the Device/DeviceController Status Byte and the lOP Status Byte.Bits 16-18. These bits of the AIO response are reserved.To ensure program compatibility with any enhancements(software and/or hardware), it is recommended that thesebits be treated as indeterminate and not used (i. e., masked).BitPositionTable 18. lOP Status ByteSignificance8 Incorrect Length. This bit is set to 1 if anincorrect length condition occurred withinthe responding subchannel. An incorrectlength condition is caused by a IIchannelend" (or end of record) condition occurringbefore the device controller has a "countdone" signal from the lOP (indicating that101112Zero Byte Count Interrupt. This bit is set to 1if the interrupt on zero byte count flag is 1and zero byte count is detected.Channel End Interrupt. This bit is set to 1 ifthe interrupt at channel end flag is 1 andIIchannel end ll is reported by the device tothe lOP.Unusual End Interrupt. This bit is set to 1 ifthe interrupt at unusual end flag is 1 and unusualend is reported by the device to thelOP, or if the lOP halt is signaled to the devicecontroller by the lOP.13 Write Lock Violation. This bit is set to 1 ifthe memory signaled a Write Lock Violationin the course of transmitting information fromthe device to the memory. If the HTE flagand the IUE flag are set, the operati on wi III terminate with an "l-'n'-'5'-'0! end".14 Reserved.15 Reserved.134 Input/Output Instructions
Table 19.Status Response Bits for AIO InstructionPosition and State in Register-RDevice Status ByteOperational Status Byteo 2 3 4 567 8 9 10 11 12 13 14 15 Significanceunique to the device andthe device controllerincorrect lengthtransmission data errorzero byte count interruptchannel end interruptunusual end interruptwrite lock violationreservedreservedI/O Address. Depending upon the type of device controllerresponding to the AIO instruction, the I/O addressmay be comprised either of a processor address and a singleunitdevice controller address or a processor address, amultiunit device controller address, and a device address.The subfields of the I/O address are described in Table 20.BitPositionTable 20. I/o Address (AIO Response)Significance18-20 This field contains the cluster address.21-23 This field contains the unit address.24-27 This field contains all ones.28-31 This field contains the device address.START INPUT/OUTPUT performs the following:1. Attempts to initiate an input or output operationwhetheran I/O operation is started or not is dependentupon conditions within the addressed I/o subsystem(see meanings of condition code settings).2. Specifies which lOP, channel, device controller, andinput/output device is to be selected (bits 18-31 ofthe effective virtual address of the instruction word).3. Specifies the address of the first command doublewordfor the subsequent I/O operation (bits 13-31 of generalregister 0).4. Specifies how much additional status information is tobe returned from the I/O system (R field, bits 8-11 ofinstruction word).SIDSTART INPUT/OUTPUT(Word index alignment, privileged)5. Specifies which general registers are to be loaded withthe requested status information (R field, bits 8-11, ofinstruction word).Instruction RegisterGeneral Register 06. Set MIOP in test mode by using device controller addressX'3P or X'7F'. Note that device controlleraddresses X'3F' and X'7F' are prohibited for normaloperation.General register 0 is temporari Iy dedicated during SIO instructionexecution and must contain the doubleword memoryaddress of the first command doubleword specifying theoperation to be started. The required address informationmust be in general register 0 when the SIO is executed.Input/Output Instructions 135
Page 1 and 2:
Xerox 560 ComputerReference Manual9
Page 5 and 6:
4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8:
1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11:
Many operations are performed in fl
Page 12 and 13:
Rapid Context Switching. When respo
Page 14 and 15:
2. SYSTEM ORGANIZATIONThe elements
Page 16:
FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20:
INFORMATION BOUNDARIESBasic process
Page 21 and 22:
(Maximumof eight)Core Core Core Cor
Page 23 and 24:
3. Diagnostic logic. Each memory dr
Page 25 and 26:
eference address field of the instr
Page 27 and 28:
Instruction in memory:Instruction i
Page 29 and 30:
Real-extended addressing is specifi
Page 31:
Table 1. Basic Processor Operating
Page 35 and 36:
DesignationFunctionDesignationFunct
Page 37 and 38:
InterruptStateDisarmedArmed[$Waitin
Page 39 and 40:
AddressTable 2. Interrupt Locations
Page 41 and 42:
is assumed to contain an XPSD or a
Page 43 and 44:
Table 3. Summary of Trap LocationsL
Page 45 and 46:
TRAP MASKSThe programmer may mask t
Page 47 and 48:
PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50:
Instruction Name Mnemonic FaultDeci
Page 51 and 52:
subroutine. However, with certain c
Page 53 and 54:
3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56:
CC1 is unchanged by the instruction
Page 57 and 58:
Condition code settings:2 3 4 Resul
Page 59 and 60:
Example 2, odd R field value:Before
Page 61 and 62:
significance (FS), floating zero (F
Page 63 and 64:
next sequential register after regi
Page 65 and 66:
R 1 R2 R3 MeaningoThe effective vir
Page 67 and 68:
Page 69 and 70:
MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72:
original contents of register R, re
Page 73 and 74:
Instruction NameCompare HalfwordMne
Page 75 and 76:
Page 77 and 78:
2 3 4 Result of ShiftCircular Shift
Page 79 and 80:
4. At the completion of the left sh
Page 81 and 82:
Instruction NameFloating Subtract L
Page 83 and 84:
The following table shows the possi
Page 85 and 86:
Table 8.Condition Code Settings for
Page 87 and 88:
PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107 and 108: If CC1, or CC3, or both CC1 and CC3
Page 109 and 110: appropriate memory stack locations
Page 111 and 112: II, EI) are generated by II ORing"
Page 113 and 114: In the real extended addressing mod
Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 135 and 136: Table 13.Description of I/o Instruc
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139: Table 16. Operational Status Byte (
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160: change the rate on the primary cons
Page 161 and 162: Location(hex) (dec)20 3221 3322 342
Page 163 and 164: Table 22.Diagnostic Control (P-Mode
Page 165 and 166: at its normal rate (e. g., fixed du
Page 167 and 168: SET LOW CLOCK MARGINSThis command c
Page 169 and 170: BP STATUS AND NO.Th i s group of i
Page 171 and 172: Input5MPri ntout5MFunctionStore X 1
Page 173 and 174: 6. SYSTEM CONFIGURATION CONTROLPool
Page 175 and 176: Table 25. Functions of Processor Cl
Page 177: Table 26. Functions of Memory Unit
Page 180 and 181: STANDARD 8-BIT COMPUTER CODES (EBCD
Page 182 and 183: STANDARD SYMBOL-CODE CORRESPONDENCE
Page 184 and 185: STANDARD SYMBOL-CODE CORRESPONDENCE
Page 186 and 187: TABLE OF POWERS OF SIXTEEN II162564
Page 188 and 189: HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 190 and 191:
HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 192 and 193:
HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 196 and 197:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 198 and 199:
APPENDIX B.GLOSSARY OF SYMBOLIC TER
Page 200 and 201:
TermMeaningTermMeaningWKxWrite key
Page 202 and 203:
Table C-2. Memory Unit Status Regis
Page 204 and 205:
Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
Page 206:
701 South Aviation BoulevardEI Segu
show all

1. xerox 560 computer system - The UK Mirror Service

Create successful ePaper yourself

Delete template?

Save as template?