1. xerox 560 computer system - The UK Mirror Service

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TermMeaningTermMeaningWKxWrite key - bit positions 32, 33, 34,and 35 of PSWs; they are evaluated bythe memory write-protect feature to determineaccessibility of real memory bycurrent program.Index register address value - 3-bit contentsof bit positions 12-14 (X field) ofinstruction word. In instruction word,if X = 0, no indexing is performed;X(cont .)Xln lif X f 0, indexing is performed (after indirectaddressing if indirect addressing is called for)with general registerX in current registerblock.Hexadecimal qualifier - hexadecimal value(n) is unsigned string of hexadecimal digits(0 through 9 and A through F}surrounded bysingle quotation marks and preceded by thequalifier "X" (for example, 7B0 16is writtenX?BO I •194 Appendix B
APPENDIX C.FAULT STATUS REGISTERSTable C-<strong>1.</strong> Fault Status RegistersStatus Registers - Faults Detected By:BitSystem ControlPosition Basic Processor MIOP RMP MI PI Processor0 16 PFI PFI PFI PFI PFI PFI1 17 General register Bus Check Fault BCF Mapor access- Cluster bus Parity error onparity error (BCF) protect register parity error processor buspari ty error2 18 Control register ·Control Check CCF Cluster bus Processor bus Operationparity error Fault (CCF) parity error parity error code error3 19 Internal basic processor Control Memory CMF Reserved Unrecognized Reservedbus pari ty error Fault (CMF) operation code4 20 Clusterbus parity error CMF I/o adapter ECE Reserved Reserved Reserved5 21 Processor-Detected MIE MIE Cluster bus Reserved ReservedFault flag (PDF)sequence checkfault6 22 Memory parity error Data/order Order Reserved Reserved Reservedindicator t type t7 23 Memory Interface Out indicator t Order Reserved Multiple error ReservedError (MIE)type t8 24 Processor interface Contro I Memory Reserved Reserved Control Memory Reservedsequence check Fault (CMF) Fault (CMF)fault address bit 0 address bit 09 25 Extended arithmetic CMF Reserved Reserved CMF Reserved~'"'_ ..'"'__'"' _L__ L !'_.. IL _<strong>1.</strong>1 I •• 'I~"""''1'''''''''''' I """v """llv\,,,o~ I \..IV II UUUI t::>:> on Iaddress bit 110 26 Basi c processor CMF Reserved Reserved CMF Reservedsequence check fau It address bit 2 address bit 211 27 Successfu I instruc- CMF Reserved Reserved CMF Reservedtion retry address bit 3 address bit 312 28 Control memory parity CMF Reserved Reserved CMF Reservederror (BPE module) address bit 4 address bit 413 29 Control memory parity CMF Reserved Reserved CMF Reservederror (BPF module) address bit 5 address bit 514 30 Control memory parity CMF Reserved Reserved CMF Reservederror (B PG modu Ie) address bit 6 address bit 615 31 Control memory parity CMF Reserved Reserved CMF Reservederror (BPH module) address bit 7 address bit 7tThis is a 2-bit code indicating type of service call, as follows:Bits MIOP RMP-6 7 Signifi cance Significance- -0 0 Data In Sense0 1 Data Out Write1 0 Order In Read1 1 Order Out ControlAppendix C 195
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160: change the rate on the primary cons
Page 161 and 162: Location(hex) (dec)20 3221 3322 342
Page 163 and 164: Table 22.Diagnostic Control (P-Mode
Page 165 and 166: at its normal rate (e. g., fixed du
Page 167 and 168: SET LOW CLOCK MARGINSThis command c
Page 169 and 170: BP STATUS AND NO.Th i s group of i
Page 171 and 172: Input5MPri ntout5MFunctionStore X 1
Page 173 and 174: 6. SYSTEM CONFIGURATION CONTROLPool
Page 175 and 176: Table 25. Functions of Processor Cl
Page 177: Table 26. Functions of Memory Unit
Page 180 and 181: STANDARD 8-BIT COMPUTER CODES (EBCD
Page 182 and 183: STANDARD SYMBOL-CODE CORRESPONDENCE
Page 184 and 185: STANDARD SYMBOL-CODE CORRESPONDENCE
Page 186 and 187: TABLE OF POWERS OF SIXTEEN II162564
Page 188 and 189: HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 194 and 195: HEXADECIMAL-DECIMAL FRACTION CONVER
Page 196 and 197: HEXADECIMAL-DECIMAL FRACTION CONVER
Page 198 and 199: APPENDIX B.GLOSSARY OF SYMBOLIC TER
Page 202 and 203: Table C-2. Memory Unit Status Regis
Page 204 and 205: Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
Page 206: 701 South Aviation BoulevardEI Segu
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