1. xerox 560 computer system - The UK Mirror Service

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2. SYSTEM ORGANIZATIONThe elements of this computer system include a basicprocessor (BP), input/output processors (lOPs), memory, I/odevice controllers, and devices (see Figure 1). The processorsand interfaces clustered into functional groups, interconnectedvia buses and controlled from a ConfigurationControl Panel and a System Control Processor. Elementswithin a processor cluster share an access path for intraclustercommunications. Thus, the total computer system canbe viewed functionally as a group of program-controlledprocessor clusters communicating with each other and acommon memory. Each processor cluster operates asynchronouslyand semi-independently, automatically overlappingthe operation of elements within as well as theoperation of other processor clusters for greater speed (whencircumstances permit).PROCESSOR CLUSTERSProcessors (basic processor and MIOP, for example) aregrouped functionally along with a Memory Interface (MI)and a Processor Interface (PI) into a processor cluster. Elementswithin a processor cluster share an access path (thecluster bus) to the Memory Interface, which connects to thememory system via a memory bus. The Memory Interfaceresolves contention problems and controls use of the clusterbus by the elements in the cluster.A processor communicates with processors in other processorclusters through the Processor Interface, which connects directlyto a processor bus. Via the processor bus, any processorcan communicate with or control any other processoranywhere in the system configuration.Note: Although two processor buses are provided, a ProcessorInterface can be connected to one or theother of the processor buses, but not to both at thesame time.Within a basic processor-MIOP processor cluster, the basicprocessor primari Iy performs overa II contro I and data reductiontasks whereas the MIOP performs the task associatedwith the exchange of digital information between mainmemory and selected peripheral devices. The MIOP communicateswith device controllers via the I/o bus, whichconnects to the Controller Interface (CI).3. Internal and external interrupt processing.4. External and certain internal direct I/o (DIO) control.It provides these major interfaces with other parts of thesystem:1. System console interface.2. System contro I bus interface.3. Processor bus interface.4. Interna I and externa I interrupt interfaces.5. External and certain interna I DIO interfaces.6. System clock interface.In addition to these major interfaces it provides paths forother signals including system reset, 1.024 MHz clock,power on/power off trap requests, and external real-timeclocks.Figure 1 shows the interconnection of a System Control Processorto processor clusters via a processor bus as well as interconnectionto the system console, external Direct Input/Output (DIO), and external interrupts.BASIC PROCESSORThis section describes the organization and operation of thebasic processor in terms of instruction and data formats, informationprocessing, and program control. The basic processorcomprises a fast memory and an arithmetic and controlunit as functionally shown in Figure 2.Note: Functionally associated with the basic processor bUTphysically located elsewhere are a memory map,memory access protection codes, and memory writeprotection codes. Memory control storage for thememory map and access codes is located in the MemoryInterface, and the memory control storage forthe write protection codes (write locks) is locatedin the memory. These functions are described in"Memory System", later in this chapter.SYSTEM CONTROL PROCESSORThe System Control Processor performs these primary functionsin the overall system:1 • System control.2. External Control Subsystem.GENERAL REGISTERSA fast (integrated circuit) memory consisting of ninety-six32-bit registers is used within the basic processor. A groupof 24 registers is referred to as a register block; thus, abasic processor contains four register blocks. A 2-bit controlfield (called a register block pointer) in the programstatus words (PSWs) selects the register block currently8 System Organization
MemoryUnHMemoryUnitMemoryUnitSystemControlConsoleSystemControlProcessor~~ss;- - - - ---, rCluster (Basic) 1 II I III IMemoryIInterfaceIIIIIProcessor IBus # 1 III IIProcessor I IIInterfaceI IIr--- ____ I ~ I I ~.--1---,SystemControlProcessorIIIL_[_Jr- --,1 System I Control ILC~o~JExternal InterruptsRemote Terminal Console InputsDIO BusBasicProcessorMIOProcessoq BUS 1fT T"2I I ~·uIIIIIIIII~~-;:- - - - -,C luster (I/O)MemoryInterfaceProcessorInterfaceRMPMIOPDeviceControllero~Communications.-------1 InterfaceDeviceControllerDeviceControllerLineAdapterComm.LinesLineAdapterComm.LinesDual Access OptionFigure 1. A Xerox 560 Computer System90 30 76A-l (1/74)Basic Processor 9
Page 1 and 2: Xerox 560 ComputerReference Manual9
Page 5 and 6: 4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8: 1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11: Many operations are performed in fl
Page 12 and 13: Rapid Context Switching. When respo
Page 16: FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20: INFORMATION BOUNDARIESBasic process
Page 21 and 22: (Maximumof eight)Core Core Core Cor
Page 23 and 24: 3. Diagnostic logic. Each memory dr
Page 25 and 26: eference address field of the instr
Page 27 and 28: Instruction in memory:Instruction i
Page 29 and 30: Real-extended addressing is specifi
Page 31: Table 1. Basic Processor Operating
Page 35 and 36: DesignationFunctionDesignationFunct
Page 37 and 38: InterruptStateDisarmedArmed[$Waitin
Page 39 and 40: AddressTable 2. Interrupt Locations
Page 41 and 42: is assumed to contain an XPSD or a
Page 43 and 44: Table 3. Summary of Trap LocationsL
Page 45 and 46: TRAP MASKSThe programmer may mask t
Page 47 and 48: PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50: Instruction Name Mnemonic FaultDeci
Page 51 and 52: subroutine. However, with certain c
Page 53 and 54: 3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56: CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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Condition code settings:2 3 4 Resul
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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Condition code settings:2 3 4 Resul
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
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For either memory map format and ei
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initial value plus the initial valu
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Table 9. Status Word 0Field Bits Co
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READ INTERRUPT INHIBITSThe followin
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Table 11.Read Direct Mode 9 Status
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SET ALARM INDICATORThe following co
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INPUT jOUTPUT INSTRUCTIONSThe I/o i
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Table 13.Description of I/o Instruc
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Table 15.Device Status Byte (Regist
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Table 16. Operational Status Byte (
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Table 19.Status Response Bits for A
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If CC4 = 0, the MIOP is in a normal
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2 3 4 Meaningo 0 I/o address not re
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The functions of bits within the DC
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4. Each unit-record controller (int
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Interrupt at Channel End (Bit Posit
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Transfer in Channel. A control lOCO
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Otherwise, the first word of the ne
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Depending upon the characteristics
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change the rate on the primary cons
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Location(hex) (dec)20 3221 3322 342
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Table 22.Diagnostic Control (P-Mode
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at its normal rate (e. g., fixed du
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SET LOW CLOCK MARGINSThis command c
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BP STATUS AND NO.Th i s group of i
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Input5MPri ntout5MFunctionStore X 1
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6. SYSTEM CONFIGURATION CONTROLPool
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Table 25. Functions of Processor Cl
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Table 26. Functions of Memory Unit
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STANDARD 8-BIT COMPUTER CODES (EBCD
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STANDARD SYMBOL-CODE CORRESPONDENCE
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STANDARD SYMBOL-CODE CORRESPONDENCE
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TABLE OF POWERS OF SIXTEEN II162564
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HEXADECIMAL-DECIMAL INTEGER CONVERS
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Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
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HEXADECIMAL-DECIMAL FRACTION CONVER
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APPENDIX B.GLOSSARY OF SYMBOLIC TER
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TermMeaningTermMeaningWKxWrite key
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Table C-2. Memory Unit Status Regis
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Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
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