1. xerox 560 computer system - The UK Mirror Service

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BitPosition Status SignificanceTable 24. Bit Assignments, Address Compare Register Q31 (X11 FI)0 1 Selects mapped address comparison.0 Selects unmapped address comparison.1 1 Selects address comparison during instruction access only.0 Selects address comparison for all memory cycles.2 1 Selects comparisons only during memory write cycle.0 Selects all memory cycle comparisons.3 1 Selects page comparisons.0 Selects word comparisons.4 1 System turns on audible alarm for 220 microseconds each time an Address Compare occurs{maximum frequency 1KHz}.0 Address match alarm is disabled.5 1 The processor is forced into the HALT state when an Address Compare occurs.0 Address Halt disabled.6-7 - Reserved.8-31 - Comparison address field.166 Control Commands
6. SYSTEM CONFIGURATION CONTROLPooled resources along with flexible configuration controlprovide a high degree of continuous availability. If aproblem occurs in an individual unit of a resource pool,the system may allow that unit to be isolated with a lossonly in capacity but no loss of functional capability,assuming there is an additional unit of that type in thesystem that can absorb the added load. Specialized unitscan be duplicated (with all units being normally used,where possible) and configuration controls used to divertthe input from one to the other in the event of a failure.Chapter 2 describes the system organization and Chapter 5discusses system operational control. This chapter describesthe Configuration Control Panel (CCP), which servesas the principal element for controlling and modifying theconfiguration of the system.CONFIGURATION CONTROL PANEL (CCP)The CCP provides the capability for enabling and disablingunits in the system. It accomplishes this with centrallylocated manual selection switches used for the followingfunctions:configuration control is designed in a modular manner. Asthe system grows, previously unused rows on the panel canbe used (up to the panel IS maximum of six), and an additionalpanel may be added. Two panels represent the maximumconfiguration for one endbell assembly.Note: The Configuration Control Panel does not contain--- operational controls as the System Control Paneldoes. The CCP switches are initially positionedduring system configuration and are not normallyreposi ti oned duri ng system operati on.CONFIGURATION CONTROL STATUS WORDA program may read settings of the panel switches, type ofunit, and options installed. A READ DIRECT (RD) instructionusing the chassis address of the cluster or unitas an address allows the program to determine the configurationstatus of a particular processor cluster or memoryunit, for example. (The chassis address assignment representsthe chassis ' physical location relative to the endbellassembly.) (See Figure 16.)1. Establish starting addresses for all memory units in thesystem.2. Enable or disable memory ports.3. Enable or disable individual units and clusters.The configuration control status of a panel read by theRD instruction is a 32-bit status word consisting of panelswitch settings and type information. (The RD instruction is descri bed in Chapter 3, .. Control Instructi ons" • )The logic for these program provisions resides in eachunit.4. Control the power throughout the system.The Configuration Control Panel is mounted within the endbellassembly at the end of the row of cabinets containingthe chassis assemblies for the MUs, BP, and other systemcomponents. On the outer surface of the endbell assemblyis the System Control Panel (described and illustrated inChapter 5). Access is gained to the CCP by opening thehinged endbell assembly (see Figure 16).In addition to reading configuration status informationvia a READ DIRECT (RD) instruction in a program, thestatus information may also be obtained by manual switchselection on the System Control Panel; the 32-bit statusword is displayed on a bank of lamp indicators. (SeeChapter 5 for a discussion of the System Control Panelfeatures. )A CCP has six rows of 22 toggle switches and two lamp indicatorseach. A row may control a memory unit, processorcluster, or system control processor. (See Figure 17, andTables 25 and 26.) The active logic assocIated with eachrow of switches and indicators is located within each processorcluster or memory unit itself. Above each row is amarker strip that identifies the function of each switch. TheCONFIGURATION BUSThe configuration bus connects to each processor cl uster andprovides a path for the system control processor to select andread the switch settings on the CCP for the selected unit viaan RD instruction.System Configuration Control 167
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Xerox 560 ComputerReference Manual9
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4. INPUT/OUTPUT OPERA TIO NS 142 AG
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1. XEROX 560 COMPUTER SYSTEMINTRODU
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Many operations are performed in fl
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Rapid Context Switching. When respo
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2. SYSTEM ORGANIZATIONThe elements
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FAST MEMORYARITHMETIC AND CONTROL U
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INFORMATION BOUNDARIESBasic process
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(Maximumof eight)Core Core Core Cor
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3. Diagnostic logic. Each memory dr
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eference address field of the instr
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Instruction in memory:Instruction i
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Real-extended addressing is specifi
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Table 1. Basic Processor Operating
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DesignationFunctionDesignationFunct
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InterruptStateDisarmedArmed[$Waitin
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AddressTable 2. Interrupt Locations
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is assumed to contain an XPSD or a
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Table 3. Summary of Trap LocationsL
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TRAP MASKSThe programmer may mask t
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PUSH-DOWN STACK LIMIT TRAPPush-down
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Instruction Name Mnemonic FaultDeci
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subroutine. However, with certain c
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3. INSTRUCTION REPERTOIREThis chapt
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CC1 is unchanged by the instruction
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Condition code settings:2 3 4 Resul
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Example 2, odd R field value:Before
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significance (FS), floating zero (F
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next sequential register after regi
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R 1 R2 R3 MeaningoThe effective vir
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MIMULTIPLY IMMEDIATE(Immediate oper
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original contents of register R, re
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Instruction NameCompare HalfwordMne
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2 3 4 Result of ShiftCircular Shift
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4. At the completion of the left sh
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Instruction NameFloating Subtract L
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The following table shows the possi
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Table 8.Condition Code Settings for
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PACKED DECIMAL NUMBERSAll decimal a
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DSTDECIMAL STORE(Byte index alignme
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If no indirect addressing or indexi
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Instruction NameMnemonicDesignation
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Both byte strings are C bytes in le
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of the destination byte that caused
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again present, unti I a positive or
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The new contents of register 7 are:
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traps to location X'42 1 as a resul
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If there is sufficient space in the
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If CC1, or CC3, or both CC1 and CC3
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appropriate memory stack locations
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II, EI) are generated by II ORing"
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In the real extended addressing mod
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CAll INSTRUCTIONSEach ofthe four CA
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The XPSD instruction' is used for t
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If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 135 and 136: Table 13.Description of I/o Instruc
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139 and 140: Table 16. Operational Status Byte (
Page 141 and 142: Table 19.Status Response Bits for A
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160: change the rate on the primary cons
Page 161 and 162: Location(hex) (dec)20 3221 3322 342
Page 163 and 164: Table 22.Diagnostic Control (P-Mode
Page 165 and 166: at its normal rate (e. g., fixed du
Page 167 and 168: SET LOW CLOCK MARGINSThis command c
Page 169 and 170: BP STATUS AND NO.Th i s group of i
Page 171: Input5MPri ntout5MFunctionStore X 1
Page 175 and 176: Table 25. Functions of Processor Cl
Page 177: Table 26. Functions of Memory Unit
Page 180 and 181: STANDARD 8-BIT COMPUTER CODES (EBCD
Page 182 and 183: STANDARD SYMBOL-CODE CORRESPONDENCE
Page 184 and 185: STANDARD SYMBOL-CODE CORRESPONDENCE
Page 186 and 187: TABLE OF POWERS OF SIXTEEN II162564
Page 188 and 189: HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 194 and 195: HEXADECIMAL-DECIMAL FRACTION CONVER
Page 196 and 197: HEXADECIMAL-DECIMAL FRACTION CONVER
Page 198 and 199: APPENDIX B.GLOSSARY OF SYMBOLIC TER
Page 200 and 201: TermMeaningTermMeaningWKxWrite key
Page 202 and 203: Table C-2. Memory Unit Status Regis
Page 204 and 205: Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
Page 206: 701 South Aviation BoulevardEI Segu
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