1. xerox 560 computer system - The UK Mirror Service

More documents

Recommendations

Info

PSS OperationsPLS Operationsinitial TSA - - terminal TSA = initial TSA-28+1 (RO) -27+2 (R 1) -26+3 (R2) -25+4 (R3) -24+5 (R4) -23+6 (R5) -22+7 (R6) -21+8 (R7) -20+9 (R8) -19+10 (R9) -18+11 (R10) -17+12 (Rl1 ) -16+13 (R12) -15+14 (R13) -14+15 (R14) -13+16 (R15) -12+17 -11+18 -10+19 -9+20 -8+21 -7+22 -6+23 -5+24 -4+25 (PSWl) -3+26 (PSW2) -2+27 (PSW3) t -1initial TSA +28 (PSW4) - initial TSAtAs a function of the hardware, the contents of these 8 locations are indeterminateafter a PSS instruction and ignored by a PLS instruction. Theselocations are reserved for future enhancements and must not be used.Figure 12.Typical 28-Word Portion of Memory Stack for PSS and PLS102 Push-90wn Instructions (Privileged)
appropriate memory stack locations as specified by theTSAi however, subsequent values of the Space Count areindeterminate.PSSPUSH STATUS(Doubleword index alignment, privi leged)During a PLS instruction, the Space Count is incrementedby 1 for each word pulled from the memory stack. If theSpace Count is incremented beyond a value of 32,767, bitposition 32 is set to 1 (signifying an overflow condition);however, the PLS instruction continues (i. e., no trappingoccurs).!xlaDNote: Once bit position 32 has been set to a 1, it can bereset to a 0 only by executing a Mode 0, WRITEDIRECT instruction. That is, bit position 32 cannot be reset to a 0 by the decrementing process performedduring a PSS instruction.WORD COUNTThe Word Count field (bit positions 49-63) of the StatusStack Pointer Doubleword is a lS-bit counter that may containa value of 0 through 32,767. Depending upon programmingconsiderations, the initial Word Count is aspecific value either as the result of executing a Mode 0,WRITE DIRECT instruction or as the result of executing aPSS or PLS instruction.During a PSS instruction, the Word Count is incrementedLy 1 [V 1- ~uch yvvi"d pu~hcd il.tv th~ iii\:i;;Gr'j ~t~~k. Th~~,the terminal Word Count for a PSS instruction exceeds theinitial Word Count by 28. If the Word Count valueexceeds 32,767, bit position 48 is set to a 1 (signifyingthat an overflow condition has occurred); however, thePSS instruction continues the stacking operation (i. e., notrapping occurs).If the initial Word Count for a PLS instruction is equal toor greater than 28, the Word Count is decremented by 1 foreach word pulled from the memory stack and the terminalWord Count will be 28 less than the initial Word Count.Note that if bit position 48 was set to a 1 by a PSS instructionpreviously, it can not be reset to a 0 by the decrementingperformed during a PLS instruction.PUSH STATUS loads new Program Status Words from an effectivedoubleword location and stores the current environment(current Program Status Words and contents of all16 general registers) into a memory stack, as defined by theStatus Stack Pointer Doubleword. Note that the referen~eaddress points to the memory location of the new PSWs.The PSS instruction is used for three types of operations:as a normal instruction in an ongoing program; as an interruptinstruction; and as a trap instruction. The effectiveaddress of a PSS instruction is generated in one of thefollowing ways:PSS - normal instruction (see first instruction diagram)When a PSS instruction is encountered in the course ofexecution of normal programs, the effective address isgenerated according to the rules for addressing then ineffect as described by the currently active PSWs; that is, thebasic processor is operating in real, real extended, or virtualaddressing mode. The flags in bit positions 9 and 10 haveno effect and must be coded as zeros.PSS - interrupt instruction (see second instruction diagram)A PSS instruction (in an interrupt location) executed as aresult of an interrupt is called an interrupt instruction. Inthe interrupt execution sequence, the 20-bit referenceaddress is always real, independent of the map invokingbit in the PSWs. There is no indexing possible since thedesi gnator fi e ld is preempted by the reference address.Indirect addressing is permitted with precisely the sameconstraints. The indirect address word contains a 20-bitreal address with the same properties as the reference addressdescribed above. The flags in bit positions 9 and 10have no effect and must be coded as zeros.If the initial Word Count for a PLS instruction is equal tozero, the parameters within the Status Stack Pointer Doublewordare neither effective nor affected by the PLS instruction.However, default PSWs are loaded from real memorylocations 2 and 3.If the initial Word Count for a PLS instruction is less than 28and not equal to zero, the other parameters of the StatusStack Pointer Doubleword are not effective and none of theparameters are affected by the PLS instruction. Instead theBP traps to location X'4D ' (instruction exception trap) andTCC2 is set.PSS - trap instruction (see second instruction diagram)A PSS instruction (in a trap location) executed as a resu Itof a trap entry operation is called a trap instruction. In atrap execution sequence, the 20-bit reference address may beeither a real address or a virtual address according to themap invoking bit in the PSWs. There is no indexing possiblesince the index field is used for addressing. If indirectaddressing is specified, the effective address is generatedaccording to the rules for addressing then in effect as describedby the currently active PSWs. Bit positions 9 and 10must be coded as zeros.Push-Down Instructions (Privileged) 103
Page 1 and 2:
Xerox 560 ComputerReference Manual9
Page 5 and 6:
4. INPUT/OUTPUT OPERA TIO NS 142 AG
Page 7 and 8:
1. XEROX 560 COMPUTER SYSTEMINTRODU
Page 10 and 11:
Many operations are performed in fl
Page 12 and 13:
Rapid Context Switching. When respo
Page 14 and 15:
2. SYSTEM ORGANIZATIONThe elements
Page 16:
FAST MEMORYARITHMETIC AND CONTROL U
Page 19 and 20:
INFORMATION BOUNDARIESBasic process
Page 21 and 22:
(Maximumof eight)Core Core Core Cor
Page 23 and 24:
3. Diagnostic logic. Each memory dr
Page 25 and 26:
eference address field of the instr
Page 27 and 28:
Instruction in memory:Instruction i
Page 29 and 30:
Real-extended addressing is specifi
Page 31:
Table 1. Basic Processor Operating
Page 35 and 36:
DesignationFunctionDesignationFunct
Page 37 and 38:
InterruptStateDisarmedArmed[$Waitin
Page 39 and 40:
AddressTable 2. Interrupt Locations
Page 41 and 42:
is assumed to contain an XPSD or a
Page 43 and 44:
Table 3. Summary of Trap LocationsL
Page 45 and 46:
TRAP MASKSThe programmer may mask t
Page 47 and 48:
PUSH-DOWN STACK LIMIT TRAPPush-down
Page 49 and 50:
Instruction Name Mnemonic FaultDeci
Page 51 and 52:
subroutine. However, with certain c
Page 53 and 54:
3. INSTRUCTION REPERTOIREThis chapt
Page 55 and 56:
CC1 is unchanged by the instruction
Page 57 and 58: Condition code settings:2 3 4 Resul
Page 59 and 60: Example 2, odd R field value:Before
Page 61 and 62: significance (FS), floating zero (F
Page 63 and 64: next sequential register after regi
Page 65 and 66: R 1 R2 R3 MeaningoThe effective vir
Page 69 and 70: MIMULTIPLY IMMEDIATE(Immediate oper
Page 71 and 72: original contents of register R, re
Page 73 and 74: Instruction NameCompare HalfwordMne
Page 77 and 78: 2 3 4 Result of ShiftCircular Shift
Page 79 and 80: 4. At the completion of the left sh
Page 81 and 82: Instruction NameFloating Subtract L
Page 83 and 84: The following table shows the possi
Page 85 and 86: Table 8.Condition Code Settings for
Page 87 and 88: PACKED DECIMAL NUMBERSAll decimal a
Page 89 and 90: DSTDECIMAL STORE(Byte index alignme
Page 91 and 92: If no indirect addressing or indexi
Page 93 and 94: Instruction NameMnemonicDesignation
Page 95 and 96: Both byte strings are C bytes in le
Page 97 and 98: of the destination byte that caused
Page 99 and 100: again present, unti I a positive or
Page 101 and 102: The new contents of register 7 are:
Page 103 and 104: traps to location X'42 1 as a resul
Page 105 and 106: If there is sufficient space in the
Page 107: If CC1, or CC3, or both CC1 and CC3
Page 111 and 112: II, EI) are generated by II ORing"
Page 113 and 114: In the real extended addressing mod
Page 115 and 116: CAll INSTRUCTIONSEach ofthe four CA
Page 117 and 118: The XPSD instruction' is used for t
Page 119 and 120: If (I)1O = 0, trap or interrupt ins
Page 121 and 122: For either memory map format and ei
Page 123 and 124: initial value plus the initial valu
Page 125 and 126: Table 9. Status Word 0Field Bits Co
Page 127 and 128: READ INTERRUPT INHIBITSThe followin
Page 129 and 130: Table 11.Read Direct Mode 9 Status
Page 131 and 132: SET ALARM INDICATORThe following co
Page 133 and 134: INPUT jOUTPUT INSTRUCTIONSThe I/o i
Page 135 and 136: Table 13.Description of I/o Instruc
Page 137 and 138: Table 15.Device Status Byte (Regist
Page 139 and 140: Table 16. Operational Status Byte (
Page 141 and 142: Table 19.Status Response Bits for A
Page 143 and 144: If CC4 = 0, the MIOP is in a normal
Page 145 and 146: 2 3 4 Meaningo 0 I/o address not re
Page 147 and 148: The functions of bits within the DC
Page 149 and 150: 4. Each unit-record controller (int
Page 151 and 152: Interrupt at Channel End (Bit Posit
Page 153 and 154: Transfer in Channel. A control lOCO
Page 155 and 156: Otherwise, the first word of the ne
Page 157 and 158: Depending upon the characteristics
Page 159 and 160:
change the rate on the primary cons
Page 161 and 162:
Location(hex) (dec)20 3221 3322 342
Page 163 and 164:
Table 22.Diagnostic Control (P-Mode
Page 165 and 166:
at its normal rate (e. g., fixed du
Page 167 and 168:
SET LOW CLOCK MARGINSThis command c
Page 169 and 170:
BP STATUS AND NO.Th i s group of i
Page 171 and 172:
Input5MPri ntout5MFunctionStore X 1
Page 173 and 174:
6. SYSTEM CONFIGURATION CONTROLPool
Page 175 and 176:
Table 25. Functions of Processor Cl
Page 177:
Table 26. Functions of Memory Unit
Page 180 and 181:
STANDARD 8-BIT COMPUTER CODES (EBCD
Page 182 and 183:
STANDARD SYMBOL-CODE CORRESPONDENCE
Page 184 and 185:
STANDARD SYMBOL-CODE CORRESPONDENCE
Page 186 and 187:
TABLE OF POWERS OF SIXTEEN II162564
Page 188 and 189:
HEXADECIMAL-DECIMAL INTEGER CONVERS
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 196 and 197:
HEXADECIMAL-DECIMAL FRACTION CONVER
Page 198 and 199:
APPENDIX B.GLOSSARY OF SYMBOLIC TER
Page 200 and 201:
TermMeaningTermMeaningWKxWrite key
Page 202 and 203:
Table C-2. Memory Unit Status Regis
Page 204 and 205:
Y OYf'lV r'f'lrnf'lrtil"\n'''' ....
Page 206:
701 South Aviation BoulevardEI Segu
show all

1. xerox 560 computer system - The UK Mirror Service

Create successful ePaper yourself

Delete template?

Save as template?