1. xerox 560 computer system - The UK Mirror Service

1st Priority 2nd Priority 3rd PriorityInternal External Counter-Override Override Equals-ZeroInterrupts Interrupts Interrupts4th Priority 5th Priority 6th PriorityExternalExternalI/o Interrupts Group 2 Group 4InterruptsInterrupts7th PriorityExternalGroup 5InterruptsFigure 11. Interrupt Priority ChainInternal Override Group (Locations X'52 1 through X'571).The six interrupt levels of thi!> group always have the highestpriority in the system. The four count-pulse interrupt levelsare triggered by pulses from clock sources. Counter 4 hasa constant frequency of 500 Hz. Counters 1, 2, and 3 canbe individua IIy set to any of four manually switchable frequencies- the commercial line frequency, 500 Hz, 2000 Hz,or a user-supplied external signal - that may be differentfor each counter. Each of the count pulse interrupt locationsmust contain one of the modify and test instructions(MTB, MTH, or MTW), an XPSD, or a PSS instruction.H/'-_._ l.'- ____ J!C! __ l.! __ f_C .. L _ _ CC __ L! .• _ L .. L_ L_IC ... __ J __VYIII::I1 1111:: IIIUUIII~UIIUIi \UI 1111:: 1::111::~IIVI:: Uyll::, IIUIIVVUIU, UIword) causes a zero result, the appropriate counter-equalszerointerrupt level (see "Counter-Equals-Zero Group") istriggered.Note: Count pulse interrupt level 4 is a subjective timecounter with the following special attribute: Whenthe instruction in location X '55 1 is executed as theresult of an interrupt, it must be an MTB, MTH, orMTW; otherwise, an instruction exception trap(X '40') will occur.The internal override group also contains a processor faultand a memory fault interrupt level. Both locations norma IIycontain an XPSD or a PSS instruction. The processor faultinterrupt level is triggered by a signal when certain faultconditions are detected. A POLR instruction must be usedto reset the fault. The memory fault interrupt level istriggered by a signal that the memory generates when itdetects certain fault conditions. An LMS instruction mustbe used to reset the fault. (See "Trap System" later inthis chapter for further information on processor and memoryfaults.)Counter-Equals-Zero Group (Locations X 158 1 through X '5B ').Each interrupt I eve lin the counter-equa Is-zero group is associatedwith a corresponding count-pulse interrupt level inthe internal override group. When the execution of a mod-!c.. __ J L __ L ! __.L_•• _L! __ :_ .. L ___•. _ ..__•. 1 __ !_j.___.._j. 1 ___.. : __Ily UIIU IC;)I III;)IIU~IIUII III IIIC ~UUIII-I"UI;)C IIIICIIUI"I IU~UIIUIIcauses a zero result in the effective byte, halfword, or wordlocation, the corresponding counter-equals-zero interruptlevel is triggered. The counter-equals-zero interrupt locationsnormally contain an XPSD or a PSS instruction andthey can be i nh ib i ted or permitted as a group. If bit 37(CI) of the current PSW contains a zero, the counter-equalszerointerrupt levels are allowed to interrupt the programbeing executed. If the CI bit contains a one, the counterequals-zerointerrupt levels are inhibited from being allowedto interrupt the program. These interrupt levels wait untilthe C I bit is reset to zero and then interrupt the program accordingto priority.Input/Output Group (Locations X '5C through X '5F'). Thisinterrupt group comprises the input/output (I/O) interruptlevel, the control panel interrupt level, and two levels reservedfor future use. The I/O interrupt level accepts interruptsigna Is from the I/o system. The I/O interrupt location34 Centralized Interrupts