1. xerox 560 computer system - The UK Mirror Service

system. If the basic processor is in the map mode, theprogram address wi II already have been modified by thememory map to generate an actual (but nonexistent) address.(See Table 5 for possible changes to registers andmemory locations later in this chapter.) The operation ofthe X PSD or PSS in location X 140 1 is as follows:1. Store the current PSWs.2. Store general registers if PSS.3. Load the new PSWs.without changing protected memory and traps to locationX'40 I • Refer to Table 5 for possible changes to registersand memory locations. (The virtual page address that causedthe violation is in the fourth PSW word.) The operation ofthe XPSD or PSS in trap location X'40 1 is as follows:1 • Store the current PSWs.2. Store general registers if PSS.3. Load the new PSWs.4. Modify the new PSWs.a. Set CC2 to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the XPSD or PSS instructioncontains a one, the program counter is incrementedby four. If AI contains a zero, the programcounter remains unchanged from the value loadedfrom memory.4. Modify the new PSWs.a. Set CC4 to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the XPSD or PSS containsa one, the program counter is incremented by one.If AI contains a zero, the program counter remainsunchanged from the va lue loaded from memory.PRIVILEGED INSTRUCTION IN SLAVE MODEAn attempt to execute a privi leged instruction while thebasic processor is in the slave mode causes a trap to locationX'40 ' before the privi leged operation is performed.No general registers or memory locations are changed, andthe PSWs point to the instruction trapped. The operationof the XPSD or PSS in trap location X'40 ' is as follows:1 • Store the current PSWs.2. Store general registers if PSS.3. Load the new PS'vVs.a. Set CC3 to one. The other condition code bitsremain unchanged from the values loaded frommemory.b. If bit position 9 (AI) of the XPSD or PSS containsa one, the program counter is implemented by two.If AI contains a zero, the program counter remainsunchanged from the values loaded from memory.MEMORY PROTECTION VIOLA nONA memory protection violation occurs because of a memorymap access control bit violation (by a program executedin slave mode or master-protected mode using the memorymap). When memory protection violation occurs, thebasic processor aborts execution of the current instructionWRITE LOCK VIOLATIONA memory write lock violation occurs when an instruction(program in master, master-protected, or slave mode) triesto alter the contents of a write-protected memory page. Ifa write lock violation occurs, the basic processor aborts executionof the current instruction without changing protectedmemory and traps to location X 140 1 • (Refer to Table 5 forpossible changes to registers and memory locations.) (Thevirtual page address that caused the violation is the fourthPSW word.) The operation of the XPSD or PSS in trap locationX'40' is as follows:1 . Store the current PSWs.2. Store genera I reg is ters if PSS.3. Load the new PSWs.4. Modify the new PSWs.a. Set CC3 and CC4 to ones. The other conditioncode bits remain unchanged from the values loadedfrom memory.b. If bit position 9 (AI) of the X PSD or PSS containsa one, the program counter is incremented bythree. If AI contains a zero, the program counterremains unchanged from the value loaded frommemory.40 Trap System