BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

CHAPTER 7: Benchmark Test ResultsA series of benchmark tests [26] have been performed to check the model robustness,accuracy and performance. Although not all the benchmark test results are included in thischapter, the most important ones are demonstrated.7.1 Benchmark Test TypesTable 7-1 lists the various benchmark test conditions and associated figure numberincluded in this section. Notice that for each plot, smooth transitions are apparentfor current, transconductance, and source to drain resistance for all transitionregions regardless of bias conditions.Device Size Bias Conditions NotesFigureNumberW/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-1W/L=20/5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-2W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Log scale 7-3W/L=20/0.5 Ids vs. Vgs @ Vbs=0V; Vds=0.05, 3.3V Linear scale 7-4W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-5W/L=20/5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V; W/L=20/5Linear scale 7-6W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Log scale 7-7W/L=20/0.5 Ids vs. Vgs @ Vds=0.05V; Vbs=0 to -3.3V Linear scale 7-8W/L=20/5 Gm/Ids vs. Vgs @ Vds=0.05V, 3-3V; Vbs=0V Linear scale 7-9BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 7-1