BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

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Effective Channel Length and WidthdW = dW ' + dW VdW ' = WintgW+LlW lngsteffW+W+ dWwWwnb( Φ −V− Φ )sW+L WwlW ln WwnLlLwdL = L + + +L LwnL W Lbseffwlint ln LlnLwnLWs(2.8.3)(2.8.4)These complicated formulations require some explanation. From Eq. (2.8.3), thevariable W int models represents the tradition manner from which "delta W" isextracted (from the intercepts of straights lines on a 1/R ds vs. W drawn plot). Theparameters dW g and dW b have been added to account for the contribution of bothfront gate and back side (substrate) biasing effects. For dL, the parameter L intrepresents the traditional manner from which "delta L" is extracted (mainly fromthe intercepts of lines from a R ds vs. L drawn plot).The remaining terms in both dW and dL are included for the convenience of theuser. They are meant to allow the user to model each parameter as a function ofW drawn , L drawn and their associated product terms. In addition, the freedom tomodel these dependencies as other than just simple inverse functions of W and L isalso provided for the user. For dW, they are Wln and Wwn. For dL they are Lln andLwn.By default all of the above geometrical dependencies for both dW and dL areturned off. Again, these equations are provided for the convenience of the user. Assuch, it is up to the user to adopt the correct extraction strategy to ensure properuse.2-32 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley
Poly Gate Depletion Effect2.9 Poly Gate Depletion EffectWhen a gate voltage is applied to a heavily doped poly-silicon gate, e.g. NMOSwith n + poly-silicon gate, a thin depletion layer will be formed at the interfacebetween the poly-silicon and gate oxide. Although this depletion layer is very thindue to the high doping concentration of the poly-Si gate, its effect cannot beignored in the 0.1µm regime since the gate oxide thickness will also be very small,possibly 50Å or thinner.Figure 2-7 shows an NMOSFET with a depletion region in the n + poly-silicongate. The doping concentration in the n + poly-silicon gate is N gate and the dopingconcentration in the substrate is N sub . The gate oxide thickness is T ox . The depletionwidth in the poly gate is X p . The depletion width in the substrate is X d . If weassume the doping concentration in the gate is infinite, then no depletion regionwill exist in the gate, and there would be one sheet of positive charge whosethickness is zero at the interface between the poly-silicon gate and gate oxide.In reality, the doping concentration is, of course, finite. The positive charge nearthe interface of the poly-silicon gate and the gate oxide is distributed over a finitedepletion region with thickness X p . In the presence of the depletion region, thevoltage drop across the gate oxide and the substrate will be reduced, because partof the gate voltage will be dropped across the depletion region in the gate. Thatmeans the effective gate voltage will be reduced.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-33
Page 1 and 2: BSIM3v3.2.2 MOSFET ModelUsers’ Ma
Page 5 and 6: Table of ContentsCHAPTER 1: Introdu
Page 7 and 8: CHAPTER 6: Parameter Extraction 6-1
Page 9 and 10: APPENDIX C: References C-1APPENDIX
Page 11 and 12: CHAPTER 1: Introduction1.1 General
Page 14 and 15: Non-Uniform Doping and Small Channe
Page 28 and 29: Mobility Modelµeffµ=01 + ( E E )e
Page 30 and 31: Bulk Charge Effectµ eff Ev = , E <
Page 32 and 33: Strong Inversion Drain Current (Lin
Page 34 and 35: Strong Inversion Current and Output
Page 42 and 43: Subthreshold Drain CurrentV1 PSCBE2
Page 46 and 47: Poly Gate Depletion EffectNgateFigu
Page 48 and 49: Poly Gate Depletion Effect1.00Tox=8
Page 50 and 51: Poly Gate Depletion EffectBSIM3v3.2
Page 52 and 53: Poly Gate Depletion Effect2-40 BSIM
Page 54 and 55: Unified Channel Charge Density Expr
Page 56 and 57: Unified Channel Charge Density Expr
Page 58 and 59: Unified Mobility Expression∆QVF(
Page 60 and 61: Unified Linear Current ExpressionI=
Page 62 and 63: Unified Vdsat ExpressionLet V ds =V
Page 64 and 65: Single Current Expression for All O
Page 67 and 68: KAPITEL 7RESULTAT OCH REKOMMENDATIO
Page 69 and 70: CHAPTER 4: Capacitance ModelingAccu
Page 71 and 72: Geometry Definition for C-V Modelin
Page 73 and 74: Methodology for Intrinsic Capacitan
Page 83 and 84: Charge-Thickness Capacitance Modelp
Page 85 and 86: Charge-Thickness Capacitance Modelw
Page 87 and 88: Extrinsic CapacitanceFigure 4-4 ill
Page 89 and 90: Extrinsic Capacitance2( V + δ ) 4
Page 91 and 92: CHAPTER 5: Non-Quasi Static Model5.
Page 93 and 94: Model FormulationFigure 5-1. Quasi-
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Model Formulationwhere elm is the E
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Model Formulationwhere i represents
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CHAPTER 6: Parameter ExtractionPara
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Extraction ProcedureWOrthogonal Set
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Extraction ProcedureInitial Guess o
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Extraction Procedureoptimization. (
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Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 6: Parameter ExtractionPara
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Extraction ProcedureWOrthogonal Set
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Extraction ProcedureInitial Guess o
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Extraction Procedureoptimization. (
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Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 7: Benchmark Test ResultsA
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Benchmark Test ResultsIds (A)1.E-02
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Benchmark Test Resultsgm/Ids (mho/A
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CHAPTER 8: Noise Modeling8.1 Flicke
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Flicker NoiseNlC=ox( V −V− min(
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Noise Model Flag8.3 Noise Model Fla
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CHAPTER 9: MOS Diode Modeling9.1 Di
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Diode IV ModelJssw= Js0sw⎛ E⎜
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MOS Diode Capacitance Model9.1.3 Mo
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MOS Diode Capacitance Model(9.18)Cj
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MOS Diode Capacitance Model(9.26)Cj
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MOS Diode Capacitance Model(9.32)
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APPENDIX A: Parameter ListA.1 Model
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DC ParametersSymbolsused inequation
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C-V Model ParametersSymbolsused ine
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dW and dL ParametersA.5 dW and dL P
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Temperature ParametersSymbolsused i
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Process ParametersSymbolsused inequ
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Model Parameter NotesK2( γ1−γ)(
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Model Parameter NotesCgdo = dlc * C
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APPENDIX B: Equation ListB.1 I-V Mo
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I-V ModelC C V C V D L effDL effdsc
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I-V ModelEsatsat= 2νµ effB.1.5 Ef
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I-V ModelB.1.8 Polysilicon Depletio
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Capacitance Model EquationsTRdsw( T
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Capacitance Model EquationsB.2.2.2
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Capacitance Model EquationsQ inv= 0
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Capacitance Model Equationsif (V ds
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Capacitance Model Equations⎡Q W L
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Capacitance Model EquationsVgsteff
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Capacitance Model Equations(i) 50/5
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Capacitance Model EquationsAbulk0
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Capacitance Model Equations(3) capM
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Capacitance Model EquationsδQsub=
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APPENDIX C: References[1] G.S. Gild
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[18] M.C. Jeng, "Design and Modelin
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[35] K.K. Hung et al, “A Physics-
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APPENDIX D: Model Parameter Binning
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AC and Capacitance ParametersD.3 AC
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NQS ParametersD.4 NQS ParametersSym
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Temperature ParametersD.6 Temperatu
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Process ParametersSymbolsused inequ
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