BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

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Benchmark Test ResultsIds (A)9.E-038.E-037.E-036.E-035.E-034.E-033.E-032.E-031.E-030.E+00W/L=20/0.5Tox=9nmVbs=0VVgs=3.3VVgs=1.084V0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5Vds (V)Figure 7-15. Same as Figure 7-14 but for a short channel device.Rout (Ohm)2.0E+051.8E+051.6E+051.4E+051.2E+051.0E+058.0E+046.0E+044.0E+042.0E+040.0E+00W/L=20/0.5Tox=9 nmVbs=0VVgs=1.084VVgs=3.3V0.0 1.0 2.0 3.0 4.0Vds (V)Figure 7-16. Continuous and non-negative R out behavior.7-10 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley
CHAPTER 8: Noise Modeling8.1 Flicker NoiseSymbolsused inequation8.1.1 ParametersThere exist two models for flicker noise modeling. One is called SPICE2flicker noise model; the other is BSIM3 flicker noise model [35-36]. Theflicker noise model parameters are listed in Table 8-1.Symbolsused inSPICEDescription Default UnitNoia noia Noise parameter A (NMOS) 1e20 none(PMOS) 9.9e18Noib noib Noise parameter B (NMOS) 5e4 none(PMOS) 2.4e3Noic noic Noise parameter C (NMOS) -1.4e-12 none(PMOS) 1.4e-12Em em Saturation field 4.1e7 V/mAf af Flick noise exponent 1 noneEf ef Flicker noise frequency1 noneexponentKf kf Flicker noise coefficient 0 noneTable 8-1. Flicker noise model parameters.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 8-1
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BSIM3v3.2.2 MOSFET ModelUsers’ Ma
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Table of ContentsCHAPTER 1: Introdu
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CHAPTER 6: Parameter Extraction 6-1
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APPENDIX C: References C-1APPENDIX
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CHAPTER 1: Introduction1.1 General
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Non-Uniform Doping and Small Channe
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Mobility Modelµeffµ=01 + ( E E )e
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Bulk Charge Effectµ eff Ev = , E <
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Strong Inversion Drain Current (Lin
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Strong Inversion Current and Output
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Subthreshold Drain CurrentV1 PSCBE2
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Effective Channel Length and Widthd
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Poly Gate Depletion EffectNgateFigu
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Poly Gate Depletion Effect1.00Tox=8
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Poly Gate Depletion EffectBSIM3v3.2
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Poly Gate Depletion Effect2-40 BSIM
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Unified Channel Charge Density Expr
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Unified Channel Charge Density Expr
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Unified Mobility Expression∆QVF(
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Unified Linear Current ExpressionI=
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Unified Vdsat ExpressionLet V ds =V
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Single Current Expression for All O
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KAPITEL 7RESULTAT OCH REKOMMENDATIO
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CHAPTER 4: Capacitance ModelingAccu
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Geometry Definition for C-V Modelin
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Methodology for Intrinsic Capacitan
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Charge-Thickness Capacitance Modelp
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Charge-Thickness Capacitance Modelw
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Extrinsic CapacitanceFigure 4-4 ill
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Extrinsic Capacitance2( V + δ ) 4
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CHAPTER 5: Non-Quasi Static Model5.
Page 93 and 94: Model FormulationFigure 5-1. Quasi-
Page 95 and 96: Model Formulationwhere elm is the E
Page 97 and 98: Model Formulationwhere i represents
Page 99 and 100: CHAPTER 6: Parameter ExtractionPara
Page 101 and 102: Extraction ProcedureWOrthogonal Set
Page 103 and 104: Extraction ProcedureInitial Guess o
Page 105 and 106: Extraction Procedureoptimization. (
Page 107 and 108: Extraction ProcedureStep 7Extracted
Page 109 and 110: Extraction ProcedureB0, B1Fitting T
Page 111 and 112: Extraction ProcedureStep 20Extracte
Page 113 and 114: Notes on Parameter Extraction6.4.2
Page 115 and 116: Notes on Parameter ExtractionnC-1.
Page 117 and 118: CHAPTER 6: Parameter ExtractionPara
Page 119 and 120: Extraction ProcedureWOrthogonal Set
Page 121 and 122: Extraction ProcedureInitial Guess o
Page 123 and 124: Extraction Procedureoptimization. (
Page 125 and 126: Extraction ProcedureStep 7Extracted
Page 127 and 128: Extraction ProcedureB0, B1Fitting T
Page 129 and 130: Extraction ProcedureStep 20Extracte
Page 131 and 132: Notes on Parameter Extraction6.4.2
Page 133 and 134: Notes on Parameter ExtractionnC-1.
Page 135 and 136: CHAPTER 7: Benchmark Test ResultsA
Page 137 and 138: Benchmark Test ResultsIds (A)1.E-02
Page 139 and 140: Benchmark Test ResultsIds (A)1.E-03
Page 141 and 142: Benchmark Test Resultsgm/Ids (mho/A
Page 143: Benchmark Test ResultsIds (A)8.E-05
Page 147 and 148: Flicker NoiseNlC=ox( V −V− min(
Page 149 and 150: Noise Model Flag8.3 Noise Model Fla
Page 151 and 152: CHAPTER 9: MOS Diode Modeling9.1 Di
Page 153 and 154: Diode IV ModelJssw= Js0sw⎛ E⎜
Page 155 and 156: MOS Diode Capacitance Model9.1.3 Mo
Page 157 and 158: MOS Diode Capacitance Model(9.18)Cj
Page 159 and 160: MOS Diode Capacitance Model(9.26)Cj
Page 161 and 162: MOS Diode Capacitance Model(9.32)
Page 163 and 164: APPENDIX A: Parameter ListA.1 Model
Page 165 and 166: DC ParametersSymbolsused inequation
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Page 169 and 170: C-V Model ParametersSymbolsused ine
Page 171 and 172: dW and dL ParametersA.5 dW and dL P
Page 173 and 174: Temperature ParametersSymbolsused i
Page 175 and 176: Process ParametersSymbolsused inequ
Page 177 and 178: Model Parameter NotesK2( γ1−γ)(
Page 179 and 180: Model Parameter NotesCgdo = dlc * C
Page 181 and 182: APPENDIX B: Equation ListB.1 I-V Mo
Page 183 and 184: I-V ModelC C V C V D L effDL effdsc
Page 185 and 186: I-V ModelEsatsat= 2νµ effB.1.5 Ef
Page 187 and 188: I-V ModelB.1.8 Polysilicon Depletio
Page 189 and 190: Capacitance Model EquationsTRdsw( T
Page 191 and 192: Capacitance Model EquationsB.2.2.2
Page 193 and 194: Capacitance Model EquationsQ inv= 0
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Capacitance Model Equationsif (V ds
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Capacitance Model Equations⎡Q W L
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Capacitance Model EquationsVgsteff
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Capacitance Model Equations(i) 50/5
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Capacitance Model EquationsAbulk0
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Capacitance Model Equations(3) capM
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Capacitance Model EquationsδQsub=
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APPENDIX C: References[1] G.S. Gild
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[18] M.C. Jeng, "Design and Modelin
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[35] K.K. Hung et al, “A Physics-
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APPENDIX D: Model Parameter Binning
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DC ParametersSymbolsused inequation
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DC ParametersSymbolsused inequation
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AC and Capacitance ParametersD.3 AC
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NQS ParametersD.4 NQS ParametersSym
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Temperature ParametersD.6 Temperatu
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Process ParametersSymbolsused inequ
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BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

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