BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

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Unified Channel Charge Density ExpressionQ= Qchsubs0 0Vgs−Vthexp( )nvt(3.1.1a)where Q 0 isQ0= qεsiNchVoffv t exp(2− )φsnvtQchs0 = Cox( Vgs −Vth)(3.1.1b)(3.1.2)In both Eqs. (3.1.1a) and (3.1.2), the parameters Q chsubs0 and Q chs0 are the channelcharge densities at the source for very small Vds. To form a unified expression, aneffective (V gs -V th ) function named V gsteff is introduced to describe the channelcharge characteristics from subthreshold to strong inversionVgsteff⎡ Vgs−Vth⎤2 nvtln⎢1+exp( ) ⎥nvt=⎣ 2 ⎦2ΦsVgs −Vth − 2Voff1+ 2 n COXexp( −)qεsiNch2 nvt(3.1.3)The unified channel charge density at the source end for both subthreshold andinversion region can therefore be written asQC Vchs0 = ox gsteff(3.1.4)Figures 3-1 and 3-2 show the smoothness of Eq. (3.1.4) from subthreshold tostrong inversion regions. The V gsteff expression will be used again in subsequentsections of this chapter to model the drain current.3-2 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley
Unified Channel Charge Density ExpressionVgsteff (V)3.02.52.01.51.00.50.0-0.5Vgsteff Functionexp[(Vgs-Vth)/n*v t]Vgs=Vth-1.0(Vgs-Vth)-1.5-1.0 -0.5 0.0 0.5 1.0 1.5 2.0V gs -V th (V)Vgs-Vth (V)Figure 3-1. The V gsteff function vs. (V gs -V th ) in linear scale.42Log(Vgsteff)0Log(Vgsteff)-2-4-6-8-10-12-14(Vgs-Vth)exp[(Vgs-Vth)/n*v t]Vgs=Vth-16-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5Vgs-Vth (V)Vgs-Vth (V)Figure 3-2. V gsteff function vs. (V gs -V th ) in log scale.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 3-3
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BSIM3v3.2.2 MOSFET ModelUsers’ Ma
Page 5 and 6: Table of ContentsCHAPTER 1: Introdu
Page 7 and 8: CHAPTER 6: Parameter Extraction 6-1
Page 9 and 10: APPENDIX C: References C-1APPENDIX
Page 11 and 12: CHAPTER 1: Introduction1.1 General
Page 14 and 15: Non-Uniform Doping and Small Channe
Page 28 and 29: Mobility Modelµeffµ=01 + ( E E )e
Page 30 and 31: Bulk Charge Effectµ eff Ev = , E <
Page 32 and 33: Strong Inversion Drain Current (Lin
Page 34 and 35: Strong Inversion Current and Output
Page 42 and 43: Subthreshold Drain CurrentV1 PSCBE2
Page 44 and 45: Effective Channel Length and Widthd
Page 46 and 47: Poly Gate Depletion EffectNgateFigu
Page 48 and 49: Poly Gate Depletion Effect1.00Tox=8
Page 50 and 51: Poly Gate Depletion EffectBSIM3v3.2
Page 52 and 53: Poly Gate Depletion Effect2-40 BSIM
Page 56 and 57: Unified Channel Charge Density Expr
Page 58 and 59: Unified Mobility Expression∆QVF(
Page 60 and 61: Unified Linear Current ExpressionI=
Page 62 and 63: Unified Vdsat ExpressionLet V ds =V
Page 64 and 65: Single Current Expression for All O
Page 67 and 68: KAPITEL 7RESULTAT OCH REKOMMENDATIO
Page 69 and 70: CHAPTER 4: Capacitance ModelingAccu
Page 71 and 72: Geometry Definition for C-V Modelin
Page 73 and 74: Methodology for Intrinsic Capacitan
Page 83 and 84: Charge-Thickness Capacitance Modelp
Page 85 and 86: Charge-Thickness Capacitance Modelw
Page 87 and 88: Extrinsic CapacitanceFigure 4-4 ill
Page 89 and 90: Extrinsic Capacitance2( V + δ ) 4
Page 91 and 92: CHAPTER 5: Non-Quasi Static Model5.
Page 93 and 94: Model FormulationFigure 5-1. Quasi-
Page 95 and 96: Model Formulationwhere elm is the E
Page 97 and 98: Model Formulationwhere i represents
Page 99 and 100: CHAPTER 6: Parameter ExtractionPara
Page 101 and 102: Extraction ProcedureWOrthogonal Set
Page 103 and 104: Extraction ProcedureInitial Guess o
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Extraction Procedureoptimization. (
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Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 6: Parameter ExtractionPara
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Extraction ProcedureWOrthogonal Set
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Extraction ProcedureInitial Guess o
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Extraction Procedureoptimization. (
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Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 7: Benchmark Test ResultsA
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Benchmark Test ResultsIds (A)1.E-02
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Benchmark Test Resultsgm/Ids (mho/A
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CHAPTER 8: Noise Modeling8.1 Flicke
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Flicker NoiseNlC=ox( V −V− min(
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Noise Model Flag8.3 Noise Model Fla
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CHAPTER 9: MOS Diode Modeling9.1 Di
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Diode IV ModelJssw= Js0sw⎛ E⎜
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MOS Diode Capacitance Model9.1.3 Mo
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MOS Diode Capacitance Model(9.18)Cj
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MOS Diode Capacitance Model(9.26)Cj
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MOS Diode Capacitance Model(9.32)
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APPENDIX A: Parameter ListA.1 Model
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DC ParametersSymbolsused inequation
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C-V Model ParametersSymbolsused ine
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dW and dL ParametersA.5 dW and dL P
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Temperature ParametersSymbolsused i
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Process ParametersSymbolsused inequ
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Model Parameter NotesK2( γ1−γ)(
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Model Parameter NotesCgdo = dlc * C
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APPENDIX B: Equation ListB.1 I-V Mo
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I-V ModelC C V C V D L effDL effdsc
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I-V ModelEsatsat= 2νµ effB.1.5 Ef
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I-V ModelB.1.8 Polysilicon Depletio
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Capacitance Model EquationsTRdsw( T
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Capacitance Model EquationsB.2.2.2
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Capacitance Model EquationsQ inv= 0
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Capacitance Model Equationsif (V ds
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Capacitance Model Equations⎡Q W L
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Capacitance Model EquationsVgsteff
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Capacitance Model Equations(i) 50/5
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Capacitance Model EquationsAbulk0
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Capacitance Model Equations(3) capM
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Capacitance Model EquationsδQsub=
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APPENDIX C: References[1] G.S. Gild
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[18] M.C. Jeng, "Design and Modelin
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[35] K.K. Hung et al, “A Physics-
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APPENDIX D: Model Parameter Binning
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AC and Capacitance ParametersD.3 AC
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NQS ParametersD.4 NQS ParametersSym
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Temperature ParametersD.6 Temperatu
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Process ParametersSymbolsused inequ
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