BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

Methodology for Intrinsic Capacitance Modelingregion relative to the channel region. A device with a large L eff and a smallparasitic resistance can have a similar current drive as another with a smaller L effbut larger R ds . In some cases L eff can be larger than the polysilicon gate lengthgiving L eff a dubious physical meaning.The L active parameter extracted from the capacitance method is a closerrepresentation of the metallurgical junction length (physical length). Due to thegraded source/ drain junction profile the source to drain length can have a verystrong bias dependence. We therefore define L active to be that measured at gate tosource/drain flat band voltage. If DWC, DLC and the newly-introduced length/width dependence parameters (Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc) are notspecified in technology files, BSIM3v3.2.2 assumes that the DC bias-independentL eff and W eff (Eqs. (2.8.1) - (2.8.4)) will be used for C-V modeling, and DWC,DLC,Llc, Lwc, Lwlc, Wlc, Wwc and Wwlc will be set equal to the values of theirDC counterparts (default values).4.3 Methodology for Intrinsic CapacitanceModeling4.3.1 Basic FormulationTo ensure charge conservation, terminal charges instead of the terminalvoltages are used as state variables. The terminal charges Q g , Q b , Q s , andQ d are the charges associated with the gate, bulk, source, and draintermianls, respectively. The gate charge is comprised of mirror chargesfrom these components: the channel inversion charge (Q inv ), accumulationcharge (Q acc ) and the substrate depletion charge (Q sub ).4-4 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley