BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

Strong Inversion Current and Output Resistance (Saturation Regime)equal to P diblc1 and D vt1 is not equal to D rout is because the gate voltagemodulates the DIBL effect. When the threshold voltage is determined, thegate voltage is equal to the threshold voltage. But in the saturation regionwhere the output resistance is modeled, the gate voltage is much larger thanthe threshold voltage. Drain induced barrier lowering may not be the sameat different gate bias. P diblc2 is usually very small (may be as small as8.0E-3). If P diblc2 is placed into the threshold voltage model, it will notcause any significant change. However it is an important parameter inV ADIBL for long channel devices, because P diblc2 will be dominant in Eq.(2.6.8) if the channel is long.2.6.3 Current Expression without Substrate Current InducedBody EffectIn order to have a continuous drain current and output resistanceexpression at the transition point between linear and saturation region, theV Asat parameter is introduced into the Early voltage expression. V Asat isthe Early Voltage at V ds = V dsat and is as follows:VAsat=(2.6.9)Esat L+ Vdsat + 2RdsvsatCoxW( Vgst − AbulkVds/ 2)1 + Abulk RdsvsatCoxWTotal Early voltage, V A , can be written as(2.6.10)VA1 1 −1= VAsat+ ( + )V VACLMADIBLBSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-27