BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

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Strong Inversion Current and Output Resistance (Saturation Regime)a = Abulk RdsCoxWvsat+ ( −1)Abulkλ2b =−( Vgst( − 1) + Abulk Esat L+3Abulk RdsCoxWvsatVgst)λ2c = Esat LVgst +2RdsCoxWvsatVgstλ = AV 1 gst + A22 1(2.5.11)The last expression for λ is introduced to account for non-saturation effectof the device. The parasitic resistance is modeled as:RdsR=dsw( 1+PrwgVgsteff+ Prwb( Φs−Vbseff− Φs)6 W( 10 W ') reff(2.5.11)The variable R dsw is the resistance per unit width, W r is a fitting parameter,P rwb and P rwg are the body bias and the gate bias coeffecients, repectively.2.6 Strong Inversion Current and OutputResistance (Saturation Regime)A typical I-V curve and its output resistance are shown in Figure 2-6. Consideringonly the drain current, the I-V curve can be divided into two parts: the linear regionin which the drain current increases quickly with the drain voltage and thesaturation region in which the drain current has a very weak dependence on thedrain voltage. The first order derivative reveals more detailed information aboutthe physical mechanisms which are involved during device operation. The outputresistance (which is the reciprocal of the first order derivative of the I-V curve)2-22 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley
Strong Inversion Current and Output Resistance (Saturation Regime)curve can be clearly divided into four regions with distinct R out vs. V dsdependences.The first region is the triode (or linear) region in which carrier velocity is notsaturated. The output resistance is very small because the drain current has a strongdependence on the drain voltage. The other three regions belong to the saturationregion. As will be discussed later, there are three physical mechanisms whichaffect the output resistance in the saturation region: channel length modulation(CLM) [4, 14], drain-induced barrier lowering (DIBL) [4, 6, 14], and the substratecurrent induced body effect (SCBE) [14, 18, 19]. All three mechanisms affect theoutput resistance in the saturation range, but each of them dominates in only asingle region. It will be shown next that channel length modulation (CLM)dominates in the second region, DIBL in the third region, and SCBE in the fourthregion.3.0142.5TriodeCLMDIBLSCBE12I ds(mA)2.01.51086R out(KOhms)1.040.520.00 1 2 3 4V ds(V)0Figure 2-6. General behavior of MOSFET output resistance.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 2-23
Page 1 and 2: BSIM3v3.2.2 MOSFET ModelUsers’ Ma
Page 5 and 6: Table of ContentsCHAPTER 1: Introdu
Page 7 and 8: CHAPTER 6: Parameter Extraction 6-1
Page 9 and 10: APPENDIX C: References C-1APPENDIX
Page 11 and 12: CHAPTER 1: Introduction1.1 General
Page 14 and 15: Non-Uniform Doping and Small Channe
Page 28 and 29: Mobility Modelµeffµ=01 + ( E E )e
Page 30 and 31: Bulk Charge Effectµ eff Ev = , E <
Page 32 and 33: Strong Inversion Drain Current (Lin
Page 36 and 37: Strong Inversion Current and Output
Page 42 and 43: Subthreshold Drain CurrentV1 PSCBE2
Page 44 and 45: Effective Channel Length and Widthd
Page 46 and 47: Poly Gate Depletion EffectNgateFigu
Page 48 and 49: Poly Gate Depletion Effect1.00Tox=8
Page 50 and 51: Poly Gate Depletion EffectBSIM3v3.2
Page 52 and 53: Poly Gate Depletion Effect2-40 BSIM
Page 54 and 55: Unified Channel Charge Density Expr
Page 56 and 57: Unified Channel Charge Density Expr
Page 58 and 59: Unified Mobility Expression∆QVF(
Page 60 and 61: Unified Linear Current ExpressionI=
Page 62 and 63: Unified Vdsat ExpressionLet V ds =V
Page 64 and 65: Single Current Expression for All O
Page 67 and 68: KAPITEL 7RESULTAT OCH REKOMMENDATIO
Page 69 and 70: CHAPTER 4: Capacitance ModelingAccu
Page 71 and 72: Geometry Definition for C-V Modelin
Page 73 and 74: Methodology for Intrinsic Capacitan
Page 83 and 84: Charge-Thickness Capacitance Modelp
Page 85 and 86:
Charge-Thickness Capacitance Modelw
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Extrinsic CapacitanceFigure 4-4 ill
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Extrinsic Capacitance2( V + δ ) 4
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CHAPTER 5: Non-Quasi Static Model5.
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Model FormulationFigure 5-1. Quasi-
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Model Formulationwhere elm is the E
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Model Formulationwhere i represents
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CHAPTER 6: Parameter ExtractionPara
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Extraction ProcedureWOrthogonal Set
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Extraction ProcedureInitial Guess o
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Extraction Procedureoptimization. (
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Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 6: Parameter ExtractionPara
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Extraction ProcedureWOrthogonal Set
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Extraction ProcedureInitial Guess o
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Extraction Procedureoptimization. (
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Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 7: Benchmark Test ResultsA
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Benchmark Test ResultsIds (A)1.E-02
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Benchmark Test Resultsgm/Ids (mho/A
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CHAPTER 8: Noise Modeling8.1 Flicke
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Flicker NoiseNlC=ox( V −V− min(
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Noise Model Flag8.3 Noise Model Fla
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CHAPTER 9: MOS Diode Modeling9.1 Di
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Diode IV ModelJssw= Js0sw⎛ E⎜
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MOS Diode Capacitance Model9.1.3 Mo
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MOS Diode Capacitance Model(9.18)Cj
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MOS Diode Capacitance Model(9.26)Cj
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MOS Diode Capacitance Model(9.32)
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APPENDIX A: Parameter ListA.1 Model
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DC ParametersSymbolsused inequation
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C-V Model ParametersSymbolsused ine
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dW and dL ParametersA.5 dW and dL P
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Temperature ParametersSymbolsused i
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Process ParametersSymbolsused inequ
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Model Parameter NotesK2( γ1−γ)(
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Model Parameter NotesCgdo = dlc * C
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APPENDIX B: Equation ListB.1 I-V Mo
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I-V ModelC C V C V D L effDL effdsc
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I-V ModelEsatsat= 2νµ effB.1.5 Ef
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I-V ModelB.1.8 Polysilicon Depletio
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Capacitance Model EquationsTRdsw( T
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Capacitance Model EquationsB.2.2.2
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Capacitance Model EquationsQ inv= 0
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Capacitance Model Equationsif (V ds
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Capacitance Model Equations⎡Q W L
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Capacitance Model EquationsVgsteff
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Capacitance Model Equations(i) 50/5
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Capacitance Model EquationsAbulk0
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Capacitance Model Equations(3) capM
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Capacitance Model EquationsδQsub=
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APPENDIX C: References[1] G.S. Gild
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[18] M.C. Jeng, "Design and Modelin
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[35] K.K. Hung et al, “A Physics-
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APPENDIX D: Model Parameter Binning
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AC and Capacitance ParametersD.3 AC
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NQS ParametersD.4 NQS ParametersSym
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Temperature ParametersD.6 Temperatu
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Process ParametersSymbolsused inequ
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