BSIM3v3.2.2 MOSFET Model - The University of Texas at Dallas

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Methodology for Intrinsic Capacitance Modelingsaturation region is assumed to be zero. This is a good approximation forlong channel devices but fails when L eff < 2 µm. If we define a drain bias,V dsat,cv , in which the channel charge becomes a constant, we will find thatV dsat,cv in general is larger than V dsat but smaller than the long channel V dsat ,given by V gt /A bulk . However, in old long channel charge models, V dsat,cv isset to V gt /A bulk independent of channel length. Consequently, C ij /L eff has nochannel length dependence (Eqs. (4.3.6), (4.37)). A pseudo short channelmodification from the long channel has been used in the past. It involvedthe parameter A bulk in the capacitance model which was redefined to beequal to V gt /V dsat , thereby equating V dsat,cv and V dsat . This overestimated theeffect of velocity saturation and resulted in a smaller channel capacitance.The difficulty in developing a short channel model lies in calculating thecharge in the saturation region. Although current continuity stipulates thatthe charge density in the saturation region is almost constant, it is difficultto calculate accurately the length of the saturation region. Moreover, due tothe exponentially increasing lateral electric field, most of the charge in thesaturation region are not controlled by the gate electrode. However, onewould expect that the total charge in the channel will exponentiallydecrease with drain bias. Experimentally,VV,< V,< V,=active →∞Agsteff ,cvdsat iv dsat cv dsat iv Lbulk(4.3.9)and V dsat,cv is modeled by the following4-8 BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley
Methodology for Intrinsic Capacitance ModelingVcdsat , =dsat,cvAbulkVgsteff ,cv⎛ CLC+ ⎛ ⎝ ⎜ ⎞1⎜⎟⎝ Lactive⎠CLE⎞⎟⎠(4.3.10a)(4.3.10b)Vgsteff,cv⎛ ⎛V= noff⋅nv⎜+⎜tln 1 exp⎝ ⎝gs−Vth−voffcv⎞⎞⎟⎟noff⋅nvt ⎠⎠Parameters noff and voffcv are introduced to better fit measured data abovesubthreshold regions. The parameter A bulk is substituted A bulk0 in the longchannel equation byAbulk⎛' = Abulk+ ⎛ ⎝ ⎜ ⎞⎜⎟⎝ Lactive⎠⎞⎟⎠(4.3.11)0 1 CLC CLE bseff(4.3.11a)Abulk⎛=⎜1+⎜ 2⎝Ks1oxΦ −Vbseff⎛⎜⎜⎝LeffA L0+ 2effXJXdepB ⎞⎞0 ⎟⎟1+ ⋅Weff' + B ⎟⎟11+KetaV⎠⎠In (4.3.11), parameters CLC and CLE are introduced to consider channellengthmodulation.BSIM3v3.2.2 Manual Copyright © 1999 UC Berkeley 4-9
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BSIM3v3.2.2 MOSFET ModelUsers’ Ma
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Table of ContentsCHAPTER 1: Introdu
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CHAPTER 6: Parameter Extraction 6-1
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APPENDIX C: References C-1APPENDIX
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CHAPTER 1: Introduction1.1 General
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Non-Uniform Doping and Small Channe
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Page 26 and 27: Non-Uniform Doping and Small Channe
Page 28 and 29: Mobility Modelµeffµ=01 + ( E E )e
Page 30 and 31: Bulk Charge Effectµ eff Ev = , E <
Page 32 and 33: Strong Inversion Drain Current (Lin
Page 34 and 35: Strong Inversion Current and Output
Page 42 and 43: Subthreshold Drain CurrentV1 PSCBE2
Page 44 and 45: Effective Channel Length and Widthd
Page 46 and 47: Poly Gate Depletion EffectNgateFigu
Page 48 and 49: Poly Gate Depletion Effect1.00Tox=8
Page 50 and 51: Poly Gate Depletion EffectBSIM3v3.2
Page 52 and 53: Poly Gate Depletion Effect2-40 BSIM
Page 54 and 55: Unified Channel Charge Density Expr
Page 56 and 57: Unified Channel Charge Density Expr
Page 58 and 59: Unified Mobility Expression∆QVF(
Page 60 and 61: Unified Linear Current ExpressionI=
Page 62 and 63: Unified Vdsat ExpressionLet V ds =V
Page 64 and 65: Single Current Expression for All O
Page 67 and 68: KAPITEL 7RESULTAT OCH REKOMMENDATIO
Page 69 and 70: CHAPTER 4: Capacitance ModelingAccu
Page 71 and 72: Geometry Definition for C-V Modelin
Page 73 and 74: Methodology for Intrinsic Capacitan
Page 75: Methodology for Intrinsic Capacitan
Page 83 and 84: Charge-Thickness Capacitance Modelp
Page 85 and 86: Charge-Thickness Capacitance Modelw
Page 87 and 88: Extrinsic CapacitanceFigure 4-4 ill
Page 89 and 90: Extrinsic Capacitance2( V + δ ) 4
Page 91 and 92: CHAPTER 5: Non-Quasi Static Model5.
Page 93 and 94: Model FormulationFigure 5-1. Quasi-
Page 95 and 96: Model Formulationwhere elm is the E
Page 97 and 98: Model Formulationwhere i represents
Page 99 and 100: CHAPTER 6: Parameter ExtractionPara
Page 101 and 102: Extraction ProcedureWOrthogonal Set
Page 103 and 104: Extraction ProcedureInitial Guess o
Page 105 and 106: Extraction Procedureoptimization. (
Page 107 and 108: Extraction ProcedureStep 7Extracted
Page 109 and 110: Extraction ProcedureB0, B1Fitting T
Page 111 and 112: Extraction ProcedureStep 20Extracte
Page 113 and 114: Notes on Parameter Extraction6.4.2
Page 115 and 116: Notes on Parameter ExtractionnC-1.
Page 117 and 118: CHAPTER 6: Parameter ExtractionPara
Page 119 and 120: Extraction ProcedureWOrthogonal Set
Page 121 and 122: Extraction ProcedureInitial Guess o
Page 123 and 124: Extraction Procedureoptimization. (
Page 125 and 126: Extraction ProcedureStep 7Extracted
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Extraction ProcedureB0, B1Fitting T
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Extraction ProcedureStep 20Extracte
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Notes on Parameter Extraction6.4.2
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Notes on Parameter ExtractionnC-1.
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CHAPTER 7: Benchmark Test ResultsA
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Benchmark Test ResultsIds (A)1.E-02
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Benchmark Test Resultsgm/Ids (mho/A
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CHAPTER 8: Noise Modeling8.1 Flicke
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Flicker NoiseNlC=ox( V −V− min(
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Noise Model Flag8.3 Noise Model Fla
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CHAPTER 9: MOS Diode Modeling9.1 Di
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Diode IV ModelJssw= Js0sw⎛ E⎜
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MOS Diode Capacitance Model9.1.3 Mo
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MOS Diode Capacitance Model(9.18)Cj
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MOS Diode Capacitance Model(9.26)Cj
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MOS Diode Capacitance Model(9.32)
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APPENDIX A: Parameter ListA.1 Model
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DC ParametersSymbolsused inequation
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C-V Model ParametersSymbolsused ine
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dW and dL ParametersA.5 dW and dL P
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Temperature ParametersSymbolsused i
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Process ParametersSymbolsused inequ
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Model Parameter NotesK2( γ1−γ)(
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Model Parameter NotesCgdo = dlc * C
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APPENDIX B: Equation ListB.1 I-V Mo
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I-V ModelC C V C V D L effDL effdsc
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I-V ModelEsatsat= 2νµ effB.1.5 Ef
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I-V ModelB.1.8 Polysilicon Depletio
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Capacitance Model EquationsTRdsw( T
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Capacitance Model EquationsB.2.2.2
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Capacitance Model EquationsQ inv= 0
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Capacitance Model Equationsif (V ds
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Capacitance Model Equations⎡Q W L
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Capacitance Model EquationsVgsteff
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Capacitance Model Equations(i) 50/5
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Capacitance Model EquationsAbulk0
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Capacitance Model Equations(3) capM
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Capacitance Model EquationsδQsub=
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APPENDIX C: References[1] G.S. Gild
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[18] M.C. Jeng, "Design and Modelin
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[35] K.K. Hung et al, “A Physics-
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APPENDIX D: Model Parameter Binning
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AC and Capacitance ParametersD.3 AC
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NQS ParametersD.4 NQS ParametersSym
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Temperature ParametersD.6 Temperatu
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Process ParametersSymbolsused inequ
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