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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005Table 3-7.CPUID AMD Feature Support (Extended Function 8000_0001h—EDX) (continued)EDXBitFeature(feature is supported if bit is set to 1)Same asFunction 1(Table 3-5) 17 Machine Check Exception. See “H<strong>and</strong>ling Machine Check Exceptions” in <strong>Volume</strong> 2. yes8 CMPXCHG8B Instruction. yes9Advanced Programmable Interrupt Controller (APIC). BIOS must enable the local APIC.See the documentation for particular implementations of the architecture.yes10 Reserved. no1112SYSCALL <strong>and</strong> SYSRET <strong>Instructions</strong>. These instructions have different implementationsthan the SYSENTER <strong>and</strong> SYSEXIT instructions indicated by bit 11 of st<strong>and</strong>ard function 1. Foradditional information, see “Fast <strong>System</strong> Call <strong>and</strong> Return” in <strong>Volume</strong> 2.Memory-Type Range Registers (MTRRs). See “Memory-Type Range Registers” in<strong>Volume</strong> 2.noyes13 Page Global Extension. See “Global Pages” in <strong>Volume</strong> 2. yes14 Machine Check Architecture. See “Machine Check Mechanism” in <strong>Volume</strong> 2. yes15Conditional Move <strong>Instructions</strong>. Indicates support for conditional move (CMOVcc) generalpurposeinstructions, <strong>and</strong>—if the on-chip x87-instruction-unit bit (bit 0) is also set—for thex87 floating-point conditional move (FCMOVcc) instructions.yes16 Page Attribute Table (PAT). See “Memory-Type Range Registers” in <strong>Volume</strong> 2. yes17 Page-Size Extensions (PSE). See “Page-Size Extensions (PSE) Bit” in <strong>Volume</strong> 2. yes18–19 Reserved. no20 No-Execute Page Protection. See “No Execute (NX) Bit” in <strong>Volume</strong> 2. no21 Reserved. no2223AMD Extensions to MMX <strong>Instructions</strong>. Indicates support for the AMD extensions to theinteger (MMX) 64-bit media instructions, including support for certain SSE <strong>and</strong> SSE2instructions. See Appendix D, “Instruction Subsets <strong>and</strong> CPUID Feature Sets,” for details.MMX <strong>Instructions</strong>. Indicates support for the integer (MMX) 64-bit media instructions. Fordetails, see Appendix D, “Instruction Subsets <strong>and</strong> CPUID Feature Sets.”noyes24 FXSAVE <strong>and</strong> FXRSTOR <strong>Instructions</strong>. See “FXSAVE <strong>and</strong> FXRSTOR <strong>Instructions</strong>” in <strong>Volume</strong> 2. yes25 Fast FXSAVE/FXRSTOR. See "FXSAVE <strong>and</strong> FXRSTOR <strong>Instructions</strong>" in <strong>Volume</strong> 2. noNote:1. If a bit has the same meaning for function 1 as it does for function 8000_0001h, the processor sets or clears the bit identicallyfor both functions.128 CPUID

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