Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologySARShift Arithmetic RightShifts the bits of a register or memory location (first operand) to the right through theCF bit by the number of bit positions in an unsigned immediate value or the CLregister (second operand). The instruction discards bits shifted out of the CF flag. Atthe end of the shift operation, the CF flag contains the last bit shifted out of the firstoperand.The SAR instruction does not change the sign bit of the target operand. For each bitshift, it copies the sign bit to the next bit, preserving the sign of the result.The processor masks the upper three bits of the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.For 1-bit shifts, the instruction clears the OF flag to 0. When the shift count is greaterthan 1, the OF flag is undefined.If the shift count is 0, no flags are modified.Although the SAR instruction effectively divides the operand by a power of 2, thebehavior is different from the IDIV instruction. For example, shifting –11(FFFFFFF5h) by two bits to the right (that is, divide –11 by 4), gives a result ofFFFFFFFDh, or –3, whereas the IDIV instruction for dividing –11 by 4 gives a result of–2. This is because the IDIV instruction rounds off the quotient to zero, whereas theSAR instruction rounds off the remainder to zero for positive dividends and tonegative infinity for negative dividends. So, for positive operands, SAR behaves likethe corresponding IDIV instruction. For negative operands, it gives the same result ifand only if all the shifted-out bits are zeroes; otherwise, the result is smaller by 1.Mnemonic Opcode DescriptionSAR reg/mem8, 1 D0 /7 Shift a signed 8-bit register or memory operand right 1 bit.SAR reg/mem8, CL D2 /7SAR reg/mem8, imm8C0 /7 ibShift a signed 8-bit register or memory operand right the numberof bits specified in the CL register.Shift a signed 8-bit register or memory operand right the numberof bits specified by an 8-bit immediate value.SAR reg/mem16, 1 D1 /7 Shift a signed 16-bit register or memory operand right 1 bit.SAR 259