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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 Technology• ib, iw, id—Specifies an immediate-oper<strong>and</strong> value. Theopcode determines whether the value is signed or unsigned.The value following the opcode, ModRM, or SIB byte iseither one byte (ib), two bytes (iw), or four bytes (id). Word<strong>and</strong> doubleword values start with the low-order byte.• +rb, +rw, +rd, +rq—Specifies a register value that is added tothe hexadecimal byte on the left, forming a one-byte opcode.The result is an instruction that operates on the registerspecified by the register code. Valid register-code values areshown in Table 2-2.• m64—Specifies a quadword (64-bit) oper<strong>and</strong> in memory.• +i—Specifies an x87 floating-point stack oper<strong>and</strong>, ST(i). Thevalue is used only with x87 floating-point instructions. It isadded to the hexadecimal byte on the left, forming a onebyteopcode. Valid values range from 0 to 7.Table 2-2.+rb, +rw, +rd, <strong>and</strong> +rq Register ValueREX.BBit 1ValueSpecified Register+rb +rw +rd +rq0 AL AX EAX RAX1 CL CX ECX RCX0or no REXPrefix2 DL DX EDX RDX3 BL BX EBX RBX4 AH, SPL 1 SP ESP RSP5 CH, BPL 1 BP EBP RBP1. See “REX Prefixes” on page 14.6 DH, SIL 1 SI ESI RSI7 BH, DIL 1 DI EDI RDIChapter 2: Instruction Overview 47

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