Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyRDMSRRead Model-Specific RegisterLoads the contents of a 64-bit model-specific register (MSR) specified in the ECXregister into registers EDX:EAX. The EDX register receives the high-order 32 bits andthe EAX register receives the low order bits. The RDMSR instruction ignores operandsize; ECX always holds the MSR number, and EDX:EAX holds the data. If a modelspecificregister has fewer than 64 bits, the unimplemented bit positions loaded intothe destination registers are undefined.This instruction must be executed at a privilege level of 0 or a general protectionexception (#GP) will be raised. This exception is also generated if a reserved orunimplemented model-specific register is specified in ECX.Use the CPUID instruction to determine if this instruction is supported.RDMSR is a serializing instruction.For more information about model-specific registers, see the documentation forvarious hardware implementations and Volume 2, System Programming.Mnemonic Opcode DescriptionRDMSR 0F 32 Copy MSR specified by ECX into EDX:EAX.Related InstructionsWRMSR, RDTSC, RDPMCrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The RDMSR instruction is not supported, as indicated by EDX bit 5returned by CPUID standard function 1 or extended function8000_0001h.General protection,#GPXX XXCPL was not 0.The value in ECX specifies a reserved or unimplemented MSRaddress.RDMSR 333