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AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4LSL—Load Segment Limit0F 03Same aslegacy mode.32 bitsZero-extends 32-bit register results to64 bits.LSS —Load SS Segment Register0F B2Same aslegacy mode.32 bitsZero-extends 32-bit register results to64 bits.LTR—Load Task Register0F 00 /3Promoted to64 bits.Operand sizefixed at 16bits.No GPR register results.References 16-byte descriptor to load64-bit base.MFENCE—Memory Fence0F AE /6Same aslegacy mode.Not relevant.No GPR register results.Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.428 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4MOV—Move898BC7Zero-extends 32-bit register resultsto 64 bits.Promoted toB8 through BF32 bits64 bits.A1 (moffset) Zero-extends 32-bit register resultsto 64 bits.Memory offsetsA3 (moffset)are address-sizedand default to 64bits.32-bit immediateis sign-extendedto 64 bits.64-bit immediate.Memory offsetsare address-sizedand default to 64bits.MOV—Move to/from Segment Registers8C8ESame aslegacy mode.32 bitsOperand sizefixed at 16bits.Zero-extends 32-bit register results to64 bits.No GPR register results.MOV(CRn)—Move to/from ControlRegisters0F 220F 20Promoted to64 bits.Operand sizefixed at 64bits.The high 32 bits of control registersdiffer in their writability and reservedstatus. See “System Resources” inVolume 2 for details.Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 429
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