Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyMnemonic Opcode DescriptionDIV reg/mem32 F7 /6DIV reg/mem64 F7 /6Perform unsigned division of EDX:EAX by the contents of a 32-bitregister or memory location and store the quotient in EAX andthe remainder in EDX.Performs unsigned division of RDX:RAX by the contents of a 64-bit register or memory location and store the quotient in RAX andthe remainder in RDX.Related InstructionsMULrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsU U U U U U21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionDivide by zero, #DERealXVirtual8086 Protected Cause of ExceptionXXThe divisor operand was 0.X X X The quotient was too large for the designated register.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.DIV 141