Volume 3: General-Purpose and System Instructions - Stanford ...

More documents

Recommendations

Info

AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)Instruction andOpcode (hex) 1Type ofOperation 2DefaultOperandSize 3For 32-BitOperand Size 4For 64-BitOperand Size 4XADD—Exchange and Add0F C1Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.XCHG—Exchange Register/Memory withRegister8790Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.XOR—Logical Exclusive OR313335Promoted to64 bits.32 bitsZero-extends 32-bit register resultsto 64 bits.81 /683 /6Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.B.3 Invalid and Reassigned Instructions in 64-Bit ModeTable B-2 lists instructions that are illegal in 64-bit mode.Attempted use of these instructions generates an invalidopcodeexception (#UD).444 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-2.Invalid Instructions in 64-Bit ModeMnemonicOpcode(hex)DescriptionAAA 37 ASCII Adjust After AdditionAAD D5 ASCII Adjust Before DivisionAAM D4 ASCII Adjust After MultiplyAAS 3F ASCII Adjust After SubtractionBOUND 62 Check Array BoundsCALL (far) 9A Procedure Call Far (far absolute)DAA 27 Decimal Adjust after AdditionDAS 2F Decimal Adjust after SubtractionINTO CE Interrupt to Overflow VectorJMP (far) EA Jump Far (absolute)LDS C5 Load DS Far PointerLES C4 Load ES Far PointerPOP DS 1F Pop Stack into DS SegmentPOP ES 07 Pop Stack into ES SegmentPOP SS 17 Pop Stack into SS SegmentPOPA, POPAD 61 Pop All to GPR Words or DoublewordsPUSH CS 0E Push CS Segment Selector onto StackPUSH DS 1E Push DS Segment Selector onto StackPUSH ES 06 Push ES Segment Selector onto StackPUSH SS 16 Push SS Segment Selector onto StackPUSHA, PUSHAD 60 Push All to GPR Words or DoublewordsRedundant Grp1 82 /2 Redundant encoding of group1 Eb,Ib opcodesSALC D6 Set AL According to CFTable B-3 lists instructions that are reassigned to differentfunctions in 64-bit mode. Attempted use of these instructionsgenerates the reassigned function.Appendix B: General-Purpose Instructions in 64-Bit Mode 445
Page 2 and 3:
© 2002, 2003, 2004, 2005 Advanced
Page 4 and 5:
AMD64 Technology 24594 Rev. 3.10 Fe
Page 6 and 7:
Page 8:
Page 12 and 13:
Page 14 and 15:
AMD64 Technology 24594—Rev. 3.10
Page 16 and 17:
Page 18 and 19:
Page 20 and 21:
Page 22 and 23:
Page 24 and 25:
Page 26 and 27:
Page 28 and 29:
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
Page 40 and 41:
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 62 and 63:
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Page 110 and 111:
Page 112 and 113:
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
Page 196 and 197:
Page 198 and 199:
Page 200 and 201:
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
Page 252 and 253:
Page 254 and 255:
Page 256 and 257:
Page 258 and 259:
Page 260 and 261:
Page 262 and 263:
Page 264 and 265:
Page 266 and 267:
Page 268 and 269:
Page 270 and 271:
Page 272 and 273:
Page 274 and 275:
Page 276 and 277:
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Page 284 and 285:
Page 286 and 287:
Page 288 and 289:
Page 290 and 291:
Page 292 and 293:
Page 294 and 295:
Page 296 and 297:
Page 298 and 299:
Page 300 and 301:
Page 302 and 303:
Page 304 and 305:
Page 306 and 307:
Page 308 and 309:
Page 310 and 311:
Page 312 and 313:
Page 314 and 315:
Page 316 and 317:
Page 318 and 319:
Page 320 and 321:
Page 322 and 323:
Page 324 and 325:
Page 326 and 327:
Page 328 and 329:
Page 330 and 331:
Page 332 and 333:
Page 334 and 335:
Page 336 and 337:
Page 338 and 339:
Page 340 and 341:
Page 342 and 343:
Page 344 and 345:
Page 346 and 347:
Page 348 and 349:
Page 350 and 351:
Page 352 and 353:
Page 354 and 355:
Page 356 and 357:
Page 358 and 359:
Page 360 and 361:
Page 362 and 363:
Page 364 and 365:
Page 366 and 367:
Page 368 and 369:
Page 370 and 371:
Page 372 and 373:
Page 374 and 375:
Page 376 and 377:
Page 378 and 379:
Page 380 and 381:
Page 382 and 383:
Page 384 and 385:
Page 386 and 387:
Page 388 and 389:
Page 390 and 391:
Page 392 and 393:
Page 394 and 395:
Page 396 and 397:
Page 398 and 399:
Page 400 and 401:
Page 402 and 403:
Page 404 and 405:
Page 406 and 407:
Page 408 and 409:
Page 410 and 411:
Page 412 and 413:
Page 414 and 415:
Page 416 and 417:
Page 418 and 419:
Page 420 and 421:
Page 422 and 423:
Page 424 and 425: AMD64 Technology 24594 Rev. 3.10 Fe
Page 524 and 525:
Page 526 and 527:
Page 528 and 529:
Page 530 and 531:
Page 532 and 533:
Page 534:
show all

Volume 3: General-Purpose and System Instructions - Stanford ...

Create successful ePaper yourself

Delete template?

Save as template?