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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 TechnologyTable A-17.SIB Memory References (continued)[rAX*8+base]Effective Address[r8*8+base]SIBscaleFieldSIBindexFieldSIB base Field 1REX.B = 0: rAX rCX rDX rBX rSP note 1 rSI rDIREX.B = 1: r8 r9 r10 r11 r12 note 1 r14 r15/0 /1 /2 /3 /4 /5 /6 /7REX.X = 0 REX.X = 1 Complete SIB Byte (hex)000 C0 C1 C2 C3 C4 C5 C6 C7[rCX*8+base] [r9*8+base] 001 C8 C9 CA CB CC CD CE CF[rDX*8+base] [r10*8+base] 010 D0 D1 D2 D3 D4 D5 D6 D7[rBX*8+base] [r11*8+base] 011 D8 D9 DA DB DC DD DE DF11[base] [r12*8+base] 100 E0 E1 E2 E3 E4 E5 E6 E7[rBP*8+base] [r13*8+base] 101 E8 E9 EA EB EC ED EE EF[rSI*8+base] [r14*8+base] 110 F0 F1 F2 F3 F4 F5 F6 F7[rDI*8+base] [r15*8+base] 111 F8 F9 FA FB FC FD FE FFNote:1. See Table A-16 on page 409 for complete specification of SIB “base” field.Appendix A: Opcode <strong>and</strong> Oper<strong>and</strong> Encodings 411

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