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AMD64 Technology 24594 Rev. 3.10 February 2005Table 2-2.REX.BBit 11+rb, +rw, +rd, and +rq Register Value (continued)Specified RegisterValue+rb +rw +rd +rq0 R8B R8W R8D R81 R9B R9W R9D R92 R10B R10W R10D R103 R11B R11W R11D R114 R12B R12W R12D R125 R13B R13W R13D R136 R14B R14W R14D R147 R15B R15W R15D R151. See “REX Prefixes” on page 14.48 Chapter 2: Instruction Overview
24594 Rev. 3.10 February 2005 AMD64 Technology2.5.3 PseudocodeDefinitionsPseudocode examples are given for the actions of severalcomplex instructions (for example, see “CALL (Near)” onpage 87). The following definitions apply to all suchpseudocode examples://///////////////////////////////////////////////////////////////////////////////// Basic Definitions/////////////////////////////////////////////////////////////////////////////////// All comments start with these double slashes.REAL_MODE = (cr0.pe=0)PROTECTED_MODE = ((cr0.pe=1) && (rflags.vm=0))VIRTUAL_MODE = ((cr0.pe=1) && (rflags.vm=1))LEGACY_MODE = (efer.lma=0)LONG_MODE = (efer.lma=1)64BIT_MODE = ((efer.lma=1) && (cs.L=1) && (cs.d=0))COMPATIBILITY_MODE = (efer.lma=1) && (cs.L=0)PAGING_ENABLED = (cr0.pg=1)ALIGNMENT_CHECK_ENABLED = ((cr0.am=1) && (eflags.ac=1) && (cpl=3))CPL = the current privilege level (0-3)OPERAND_SIZE = 16, 32, or 64 (depending on current code and 66h/rex prefixes)ADDRESS_SIZE = 16, 32, or 64 (depending on current code and 67h prefixes)STACK_SIZE = 16, 32, or 64 (depending on current code and SS.attr.B)old_RIPold_RSPold_RFLAGSold_CSold_DSold_ESold_FSold_GSold_SSRIPRSPRBPRFLAGSnext_RIPCSSSSRCDESTtemp_*= RIP at the start of current instruction= RSP at the start of current instruction= RFLAGS at the start of the instruction= CS selector at the start of current instruction= DS selector at the start of current instruction= ES selector at the start of current instruction= FS selector at the start of current instruction= GS selector at the start of current instruction= SS selector at the start of current instruction= the current RIP register= the current RSP register= the current RBP register= the current RFLAGS register= RIP at start of next instruction= the current CS descriptor, including the subfields:sel base limit attr= the current SS descriptor, including the subfields:sel base limit attr= the instruction’s Source operand= the instruction’s Destination operand// 64-bit temporary registerChapter 2: Instruction Overview 49
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