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AMD64 Technology 24594 Rev. 3.10 February 2005Table B-1.Operations and Operands in 64-Bit Mode (continued)PREFETCHlevel—Prefetch Data to CacheLevel level0F 18 /0-3PREFETCHW—Prefetch L1 Data-Cache Linefor Write0F 0D /1PUSH—Push onto StackFF /650 through 576A68Instruction andOpcode (hex) 1PUSH—Push (segment register) onto Stack0F A0 (PUSH FS)0F A8 (PUSH GS)0E (PUSH CS)1E (PUSH DS)06 (PUSH ES)16 (PUSH SS)Type ofOperation 2Same aslegacy mode.Same aslegacy mode.Promoted to64 bits.Promoted to64 bits.DefaultOperandSize 3Not relevant.Not relevant.For 32-BitOperand Size 4No GPR register results.No GPR register results.64 bits Cannot encode 664 bits Cannot encode 6INVALID IN 64-BIT MODE (invalid-opcode exception)For 64-BitOperand Size 4Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.434 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-1.Operations and Operands in 64-Bit Mode (continued)PUSHA, PUSHAD - Push All to GPR Wordsor Doublewords60PUSHF, PUSHFD, PUSHFQ—Push rFLAGSWord, Doubleword, or Quadword ontoStack9CRCL—Rotate Through Carry LeftD1 /2D3 /2C1 /2RCR—Rotate Through Carry RightD1 /3D3 /3C1 /3RDMSR—Read Model-Specific Register0F 32Instruction andOpcode (hex) 1Type ofOperation 2Promoted to64 bits.Promoted to64 bits.Promoted to64 bits.Same aslegacy mode.DefaultOperandSize 3INVALID IN 64-BIT MODE (invalid-opcode exception)64 bits Cannot encode 6 mnemonic):Pushes the 64-bitPUSHFQ (newRFLAGS register.32 bits32 bitsNot relevant.For 32-BitOperand Size 4Zero-extends 32-bit register resultsto 64 bits.Zero-extends 32-bit register resultsto 64 bits.For 64-BitOperand Size 4Uses 6-bit count.Uses 6-bit count.RDX[31:0] contains MSR[63:32],RAX[31:0] contains MSR[31:0]. Zeroextends32-bit register results to 64bits.Note:1. See “General Rules for 64-Bit Mode” on page 413, for opcodes that do not appear in this table.2. The type of operation, excluding considerations of operand size or extension of results. See “General Rules for 64-Bit Mode” onpage 413 for definitions of “Promoted to 64 bits” and related topics.3. If “Type of Operation” is 64 bits, a REX prefix is needed for 64-bit operand size, unless the instruction size defaults to 64 bits. Ifthe operand size is fixed, operand-size overrides are silently ignored.4. Special actions in 64-bit mode, in addition to legacy-mode actions. Zero or sign extensions apply only to result operands, notsource operands. Unless otherwise stated, 8-bit and 16-bit results leave the high 56 or 48 bits, respectively, of 64-bit destinationregisters unchanged. Immediates and branch displacements are sign-extended to 64 bits.5. Any pointer registers (rDI, rSI) or count registers (rCX) are address-sized and default to 64 bits. For 32-bit address size, any pointerand count registers are zero-extended to 64 bits.6. The default operand size can be overridden to 16 bits with 66h prefix, but there is no 32-bit operand-size override in 64-bit mode.Appendix B: General-Purpose Instructions in 64-Bit Mode 435
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