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AMD64 Technology 24594 Rev. 3.10 February 2005Table A-14.reg8MnemonicNotationModRM Register References, 32-Bit and 64-Bit AddressingREX.R BitModRM reg Field/0 /1 /2 /3 /4 /5 /6 /7AL CL DL BL AH/SPL CH/BPL DH/SIL BH/DILreg16 AX CX DX BX SP BP SI DIreg32 EAX ECX EDX EBX ESP EBP ESI EDIreg64 RAX RCX RDX RBX RSP RBP RSI RDImmx 0 MMX0 MMX1 MMX2 MMX3 MMX4 MMX5 MMX6 MMX7xmm XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7sReg ES CS SS DS FS GS invalid invalidcReg CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7dReg DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7reg8R8B R9B R10B R11B R12B R13B R14B R15Breg16 R8W R9W R10W R11W R12W R13W R14W R15Wreg32 R8D R9D R10D R11D R12D R13D R14D R15Dreg64 R8 R9 R10 R11 R12 R13 R14 R15mmx 1 MMX0 MMX1 MMX2 MMX3 MMX4 MMX5 MMX6 MMX7xmm XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14 XMM15sReg ES CS SS DS FS GS invalid invalidcReg CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15dReg DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15406 Appendix A: Opcode and Operand Encodings
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable A-15.ModRM Memory References, 32-Bit and 64-Bit Addressing[rAX]ModRMEffective Address 1ModRM reg Field 3modField/0 /1 /2 /3 /4 /5 /6 /7REX.B = 0 REX.B = 1 (binary) Complete ModRM Byte (hex)[r8]ModRMr/mField(binary)00 08 10 18 20 28 30 38 000[rCX] [r9] 01 09 11 19 21 29 31 39 001[rDX] [r10] 02 0A 12 1A 22 2A 32 3A 010[rBX] [r11] 03 0B 13 1B 23 2B 33 3B 01100[SIB] 4 [SIB] 4 04 0C 14 1C 24 2C 34 3C 100[RIP+disp32] or [disp32] 2 [rIP+disp32] or [disp32] 2 05 0D 15 1D 25 2D 35 3D 101[rSI] [r14] 06 0E 16 1E 26 2E 36 3E 110[rDI] [r15] 07 0F 17 1F 27 2F 37 3F 111[rAX+disp8][r8+disp8]40 48 50 58 60 68 70 78 000[rCX+disp8] [r9+disp8] 41 49 51 59 61 69 71 79 001[rDX+disp8] [r10+disp8] 42 4A 52 5A 62 6A 72 7A 010[rBX+disp8] [r11+disp8] 43 4B 53 5B 63 6B 73 7B 01101[SIB+disp8] 4 [SIB+disp8] 4 44 4C 54 5C 64 6C 74 7C 100[rBP+disp8] [r13+disp8] 45 4D 55 5D 65 6D 75 7D 101[rSI+disp8] [r14+disp8] 46 4E 56 5E 66 6E 76 7E 110[rDI+disp8] [r15+disp8] 47 4F 57 5F 67 6F 77 7F 111[rAX+disp32][r8+disp32]80 88 90 98 A0 A8 B0 B8 000[rCX+disp32] [r9+disp32] 81 89 91 99 A1 A9 B1 B9 001[rDX+disp32] [r10+disp32] 82 8A 92 9A A2 AA B2 BA 010[rBX+disp32] [r11+disp32] 83 8B 93 9B A3 AB B3 BB 01110[SIB+disp32] 4 [SIB+disp32] 4 84 8C 94 9C A4 AC B4 BC 100[rBP+disp32] [r13+disp32] 85 8D 95 9D A5 AD B5 BD 101[rSI+disp32] [r14+disp32] 86 8E 96 9E A6 AE B6 BE 110[rDI+disp32] [r15+disp32] 87 8F 97 9F A7 AF B7 BF 111Note:1. In these combinations, “disp8” and “disp32” indicate an 8-bit or 32-bit signed displacement.2. In 64-bit mode, the effective address is [RIP+disp32]. In all other modes, the effective address is [disp32]. If the address-size prefixis used in 64-bit mode to override 64-bit addressing, the [RIP+disp32] effective address is truncated after computation to 64 bits.3. See Table A-14 for complete specification of ModRM “reg” field.4. An SIB byte follows the ModRM byte to identify the memory operand.Appendix A: Opcode and Operand Encodings 407
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