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AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)CMPPSCompare Packed Single-Precision Floating-PointCMPS Compare Strings 3 BasicCMPSB Compare Strings by Byte 3 BasicCMPSDCMPSDCMPSQCMPSSCMPSWCompare Strings byDoublewordCompare Scalar Double-Precision Floating-PointCompare Strings byQuadwordCompare Scalar Single-Precision Floating-PointCompare Strings byWord333333Basic 2Long ModeBasicCMPXCHG Compare and Exchange 3 BasicCMPXCHG8BCMPXCHG16BCOMISDCOMISSCompare and ExchangeEight BytesCompare and ExchangeSixteen BytesCompare Ordered ScalarDouble-PrecisionFloating-PointCompare Ordered ScalarSingle-PrecisionFloating-Point333CMPXCHG8BCMPXCHG16BCPUID Processor Identification 3 BasicCQOInstructionMnemonic Description CPLConvert Quadword toDouble Quadword33General-PurposeLong ModeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSESSE2 2SSESSE2SSE64-BitMediax87System1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.460 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)InstructionInstruction Subsetand CPUID Feature Set(s) 1Mnemonic Description CPLGeneral-Purpose128-BitMedia64-BitMediax87SystemCVTDQ2PDConvert PackedDoubleword Integers toPacked Double-PrecisionFloating-Point3SSE2CVTDQ2PSConvert PackedDoubleword Integers toPacked Single-PrecisionFloating-Point3SSE2CVTPD2DQConvert Packed Double-Precision Floating-Pointto Packed DoublewordIntegers3SSE2CVTPD2PIConvert Packed Double-Precision Floating-Pointto Packed DoublewordIntegers3SSE2SSE2CVTPD2PSConvert Packed Double-Precision Floating-Pointto Packed Single-Precision Floating-Point3SSE2CVTPI2PDConvert PackedDoubleword Integers toPacked Double-PrecisionFloating-Point3SSE2SSE2CVTPI2PSConvert PackedDoubleword Integers toPacked Single-PrecisionFloating-Point3SSESSECVTPS2DQConvert Packed Single-Precision Floating-Pointto Packed DoublewordIntegers3SSE21. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 461
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