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AMD64 Technology 24594 Rev. 3.10 February 2005• rel16off—Signed 16-bit offset relative to the instructionpointer.• rel32off—Signed 32-bit offset relative to the instructionpointer.• segReg or sReg—Word (16-bit) operand in a segment register.• ST(0)—x87 stack register 0.• ST(i)—x87 stack register i, where i is between 0 and 7.• xmm—Double quadword (128-bit) operand in an XMMregister.• xmm1—Double quadword (128-bit) operand in an XMMregister, specified as the left-most (first) operand in theinstruction syntax.• xmm2—Double quadword (128-bit) operand in an XMMregister, specified as the right-most (second) operand in theinstruction syntax.• xmm/mem64—Quadword (64-bit) operand in a 128-bit XMMregister or memory.• xmm/mem128—Double quadword (128-bit) operand in anXMM register or memory.• xmm1/mem128—Double quadword (128-bit) operand in anXMM register or memory, specified as the left-most (first)operand in the instruction syntax.• xmm2/mem128—Double quadword (128-bit) operand in anXMM register or memory, specified as the right-most(second) operand in the instruction syntax.2.5.2 Opcode Syntax In addition to the notation shown above in “Mnemonic Syntax”on page 43, the following notation indicates the size and type ofoperands in the syntax of an instruction opcode:• /digit—Indicates that the ModRM byte specifies only oneregister or memory (r/m) operand. The digit is specified bythe ModRM reg field and is used as an instruction-opcodeextension. Valid digit values range from 0 to 7.• /r—Indicates that the ModRM byte specifies both a registeroperand and a reg/mem (register or memory) operand.• cb, cw, cd, cp—Specifies a code-offset value and possibly anew code-segment register value. The value following theopcode is either one byte (cb), two bytes (cw), four bytes(cd), or six bytes (cp).46 Chapter 2: Instruction Overview
24594 Rev. 3.10 February 2005 AMD64 Technology• ib, iw, id—Specifies an immediate-operand value. Theopcode determines whether the value is signed or unsigned.The value following the opcode, ModRM, or SIB byte iseither one byte (ib), two bytes (iw), or four bytes (id). Wordand doubleword values start with the low-order byte.• +rb, +rw, +rd, +rq—Specifies a register value that is added tothe hexadecimal byte on the left, forming a one-byte opcode.The result is an instruction that operates on the registerspecified by the register code. Valid register-code values areshown in Table 2-2.• m64—Specifies a quadword (64-bit) operand in memory.• +i—Specifies an x87 floating-point stack operand, ST(i). Thevalue is used only with x87 floating-point instructions. It isadded to the hexadecimal byte on the left, forming a onebyteopcode. Valid values range from 0 to 7.Table 2-2.+rb, +rw, +rd, and +rq Register ValueREX.BBit 1ValueSpecified Register+rb +rw +rd +rq0 AL AX EAX RAX1 CL CX ECX RCX0or no REXPrefix2 DL DX EDX RDX3 BL BX EBX RBX4 AH, SPL 1 SP ESP RSP5 CH, BPL 1 BP EBP RBP1. See “REX Prefixes” on page 14.6 DH, SIL 1 SI ESI RSI7 BH, DIL 1 DI EDI RDIChapter 2: Instruction Overview 47
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