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AMD64 Technology 24594 Rev. 3.10 February 2005ExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X XA memory address exceeded a data segment limit or was noncanonical.XThe destination operand was in a non-writable segment.X A null data segment was used to reference memory.Page fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.342 SGDT
24594 Rev. 3.10 February 2005 AMD64 TechnologySIDTStore Interrupt Descriptor Table RegisterStores the interrupt descriptor table register (IDTR) in the destination operand. Inlegacy and compatibility mode, the destination operand is 6 bytes; in 64-bit mode it is10 bytes. In all modes, operand-size prefixes are ignored.In non-64-bit mode, the lower two bytes of the operand specify the 16-bit limit and theupper 4 bytes specify the 32-bit base address.In 64-bit mode, the lower two bytes of the operand specify the 16-bit limit and theupper 8 bytes specify the 64-bit base address.This instruction is intended for use in operating system software, but it can be used atany privilege level.Mnemonic Opcode DescriptionSIDT mem16:32 0F 01 /1 Store interrupt descriptor table register to memory.SIDT mem16:64 0F 01 /1 Store interrupt descriptor table register to memory.Related InstructionsSGDT, SLDT, STR, LGDT, LIDT, LLDT, LTRrFLAGS AffectedNoneExceptionsException RealVirtual8086 Protected Cause of ExceptionInvalid opcode, #UD X X X The operand was a register.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.SIDT 343
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