Volume 3: General-Purpose and System Instructions - Stanford ...

More documents

Recommendations

Info

AMD64 Technology 24594 Rev. 3.10 February 2005INT 3Interrupt to Debug VectorCalls the debug exception handler. This instruction maps to a 1-byte opcode (CC) thatraises a #BP exception. The INT 3 instruction is normally used by debug software toset instruction breakpoints by replacing the first byte of the instruction opcode byteswith the INT 3 opcode.This one-byte INT 3 instruction behaves differently from the two-byte INT 3instruction (opcode CD 03) (see “INT” in Chapter 3 “General Purpose Instructions”for further information) in two ways:• The #BP exception is handled without any IOPL checking in virtual x86 mode.(IOPL mismatches will not trigger an exception.)• In VME mode, the #BP exception is not redirected via the interrupt redirectiontable. (Instead, it is handled by a protected mode handler.)Mnemonic Opcode DescriptionINT 3 CC Trap to debugger at Interrupt 3.For complete descriptions of the steps performed by INT instructions, see thefollowing:• Legacy-Mode Interrupts: “Legacy Protected-Mode Interrupt Control Transfers” inVolume 2.• Long-Mode Interrupts: “Long-Mode Interrupt Control Transfers” in Volume 2.Action// Refer to INT instruction’s Action section for the details on INT_N_REAL,// INT_N_PROTECTED, and INT_N_VIRTUAL_TO_PROTECTED.INT3_START:If (REAL_MODE)INT_N_REAL //N = 3ELSEIF (PROTECTED_MODE)INT_N_PROTECTED //N = 3ELSE // VIRTUAL_MODEINT_N_VIRTUAL_TO_PROTECTED //N = 3Related InstructionsINT, INTO, IRET304 INT 3
24594 Rev. 3.10 February 2005 AMD64 TechnologyrFLAGS AffectedIf a task switch occurs, all flags are modified; otherwise, setting are as follows:ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM 0 0 M M 021 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to one or cleared to zero is M (modified). Unaffected flags are blank. Undefinedflags are U.VirtualException Real 8086 Protected Cause of ExceptionBreakpoint, #BP X X X INT 3 instruction was executed.Invalid TSS, #TS(selector)XXAs part of a stack switch, the target stack segment selector or rSP inthe TSS was that was beyond the TSS limit.XXXXXXXXXXAs part of a stack switch, the target stack segment selector in the TSSwas beyond the limit of the GDT or LDT descriptor table.As part of a stack switch, the target stack segment selector in the TSSwas a null selector.As part of a stack switch, the target stack segment selector’s TI bit wasset, but the LDT selector was a null selector.As part of a stack switch, the target stack segment selector in the TSScontained a RPL that was not equal to its DPL.As part of a stack switch, the target stack segment selector in the TSScontained a DPL that was not equal to the CPL of the code segmentselector.Segment not present,#NP (selector)XXAs part of a stack switch, the target stack segment selector in the TSSwas not a writable segment.X X The accessed code segment, interrupt gate, trap gate, task gate, orTSS was not present.Stack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.INT 3 305
Page 2 and 3:
© 2002, 2003, 2004, 2005 Advanced
Page 4 and 5:
AMD64 Technology 24594 Rev. 3.10 Fe
Page 6 and 7:
Page 8:
Page 12 and 13:
Page 14 and 15:
AMD64 Technology 24594—Rev. 3.10
Page 16 and 17:
Page 18 and 19:
Page 20 and 21:
Page 22 and 23:
Page 24 and 25:
Page 26 and 27:
Page 28 and 29:
Page 30 and 31:
Page 32 and 33:
Page 34 and 35:
Page 36 and 37:
Page 38 and 39:
Page 40 and 41:
Page 42 and 43:
Page 44 and 45:
Page 46 and 47:
Page 48 and 49:
Page 50 and 51:
Page 52 and 53:
Page 54 and 55:
Page 56 and 57:
Page 58 and 59:
Page 60 and 61:
Page 62 and 63:
Page 64 and 65:
Page 66 and 67:
Page 68 and 69:
Page 70 and 71:
Page 72 and 73:
Page 74 and 75:
Page 76 and 77:
Page 78 and 79:
Page 80 and 81:
Page 82 and 83:
Page 84 and 85:
Page 86 and 87:
Page 88 and 89:
Page 90 and 91:
Page 92 and 93:
Page 94 and 95:
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Page 108 and 109:
Page 110 and 111:
Page 112 and 113:
Page 114 and 115:
Page 116 and 117:
Page 118 and 119:
Page 120 and 121:
Page 122 and 123:
Page 124 and 125:
Page 126 and 127:
Page 128 and 129:
Page 130 and 131:
Page 132 and 133:
Page 134 and 135:
Page 136 and 137:
Page 138 and 139:
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Page 150 and 151:
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Page 158 and 159:
Page 160 and 161:
Page 162 and 163:
Page 164 and 165:
Page 166 and 167:
Page 168 and 169:
Page 170 and 171:
Page 172 and 173:
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Page 192 and 193:
Page 194 and 195:
Page 196 and 197:
Page 198 and 199:
Page 200 and 201:
Page 202 and 203:
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Page 212 and 213:
Page 214 and 215:
Page 216 and 217:
Page 218 and 219:
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Page 238 and 239:
Page 240 and 241:
Page 242 and 243:
Page 244 and 245:
Page 246 and 247:
Page 248 and 249:
Page 250 and 251:
Page 252 and 253:
Page 254 and 255:
Page 256 and 257:
Page 258 and 259:
Page 260 and 261:
Page 262 and 263:
Page 264 and 265:
Page 266 and 267:
Page 268 and 269:
Page 270 and 271:
Page 272 and 273:
Page 274 and 275:
Page 276 and 277:
Page 278 and 279:
Page 280 and 281:
Page 282 and 283:
Page 284 and 285: AMD64 Technology 24594 Rev. 3.10 Fe
Page 384 and 385:
Page 386 and 387:
Page 388 and 389:
Page 390 and 391:
Page 392 and 393:
Page 394 and 395:
Page 396 and 397:
Page 398 and 399:
Page 400 and 401:
Page 402 and 403:
Page 404 and 405:
Page 406 and 407:
Page 408 and 409:
Page 410 and 411:
Page 412 and 413:
Page 414 and 415:
Page 416 and 417:
Page 418 and 419:
Page 420 and 421:
Page 422 and 423:
Page 424 and 425:
Page 426 and 427:
Page 428 and 429:
Page 430 and 431:
Page 432 and 433:
Page 434 and 435:
Page 436 and 437:
Page 438 and 439:
Page 440 and 441:
Page 442 and 443:
Page 444 and 445:
Page 446 and 447:
Page 448 and 449:
Page 450 and 451:
Page 452 and 453:
Page 454 and 455:
Page 456 and 457:
Page 458 and 459:
Page 460 and 461:
Page 462 and 463:
Page 464 and 465:
Page 466 and 467:
Page 468 and 469:
Page 470 and 471:
Page 472 and 473:
Page 474 and 475:
Page 476 and 477:
Page 478 and 479:
Page 480 and 481:
Page 482 and 483:
Page 484 and 485:
Page 486 and 487:
Page 488 and 489:
Page 490 and 491:
Page 492 and 493:
Page 494 and 495:
Page 496 and 497:
Page 498 and 499:
Page 500 and 501:
Page 502 and 503:
Page 504 and 505:
Page 506 and 507:
Page 508 and 509:
Page 510 and 511:
Page 512 and 513:
Page 514 and 515:
Page 516 and 517:
Page 518 and 519:
Page 520 and 521:
Page 522 and 523:
Page 524 and 525:
Page 526 and 527:
Page 528 and 529:
Page 530 and 531:
Page 532 and 533:
Page 534:
show all

Volume 3: General-Purpose and System Instructions - Stanford ...

Create successful ePaper yourself

Delete template?

Save as template?