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AMD64 Technology 24594 Rev. 3.10 February 2005the 64-bit data size, these include RAX, RBX, RCX, RDX,RDI, RSI, RBP, RSP, and R8–R15.IDTRInterrupt descriptor table register.IP16-bit instruction-pointer register.LDTRLocal descriptor table register.MSRModel-specific register.r8–r15The 8-bit R8B–R15B registers, or the 16-bit R8W–R15Wregisters, or the 32-bit R8D–R15D registers, or the 64-bitR8–R15 registers.rAX–rSPThe 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers, orthe 32-bit EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESPregisters, or the 64-bit RAX, RBX, RCX, RDX, RDI, RSI,RBP, and RSP registers. Replace the placeholder r withnothing for 16-bit size, “E” for 32-bit size, or “R” for 64-bitsize.RAX64-bit version of the EAX register.RBP64-bit version of the EBP register.RBX64-bit version of the EBX register.RCX64-bit version of the ECX register.RDI64-bit version of the EDI register.RDX64-bit version of the EDX register.xxviPreface
24594 Rev. 3.10 February 2005 AMD64 TechnologyrFLAGS16-bit, 32-bit, or 64-bit flags register. Compare RFLAGS.RFLAGS64-bit flags register. Compare rFLAGS.rIP16-bit, 32-bit, or 64-bit instruction-pointer register. CompareRIP.RIP64-bit instruction-pointer register.RSI64-bit version of the ESI register.RSP64-bit version of the ESP register.SPStack pointer register.SSStack segment register.TPRTask priority register, a new register introduced in theAMD64 architecture to speed interrupt management.TRTask register.Endian OrderThe x86 and AMD64 architectures address memory using littleendianbyte-ordering. Multibyte values are stored with theirleast-significant byte at the lowest byte address, and they areillustrated with their least significant byte at the right side.Strings are illustrated in reverse order, because the addresses oftheir bytes increase from right to left.Related Documents• Peter Abel, IBM PC Assembly Language and Programming,Prentice-Hall, Englewood Cliffs, NJ, 1995.• Rakesh Agarwal, 80x86 Architecture & Programming: VolumeII, Prentice-Hall, Englewood Cliffs, NJ, 1991.Prefacexxvii
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