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AMD64 Technology 24594 Rev. 3.10 February 2005Mnemonic Opcode DescriptionSAR reg/mem16, CL D3 /7Shift a signed 16-bit register or memory operand right thenumber of bits specified in the CL register.SAR reg/mem16, imm8C1 /7 ibShift a signed 16-bit register or memory operand right thenumber of bits specified by an 8-bit immediate value.SAR reg/mem32, 1 D1 /7 Shift a signed 32-bit register or memory location 1 bit.SAR reg/mem32, CL D3 /7Shift a signed 32-bit register or memory location right thenumber of bits specified in the CL register.SAR reg/mem32, imm8C1 /7 ibShift a signed 32-bit register or memory location right thenumber of bits specified by an 8-bit immediate value.SAR reg/mem64, 1 D1 /7 Shift a signed 64-bit register or memory location right 1 bit.SAR reg/mem64, CL D3 /7Shift a signed 64-bit register or memory location right thenumber of bits specified in the CL register.SAR reg/mem64, imm8Related InstructionsC1 /7 ibShift a signed 64-bit register or memory location right thenumber of bits specified by an 8-bit immediate value.SAL, SHL, SHR, SHLD, SHRDrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsM M M U M M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.Exception RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XXThe destination operand was in a non-writable segment.A null data segment was used to reference memory.260 SAR
24594 Rev. 3.10 February 2005 AMD64 TechnologyExceptionRealVirtual8086 Protected Cause of ExceptionPage fault, #PF X X A page fault resulted from the execution of the instruction.Alignment check, #AC X X An unaligned memory reference was performed while alignmentchecking was enabled.SAR 261
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